1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_RENESAS_RTS7751R2D_H 3*4882a593Smuzhiyun #define __ASM_SH_RENESAS_RTS7751R2D_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * linux/include/asm-sh/renesas_rts7751r2d.h 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2000 Atom Create Engineering Co., Ltd. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Renesas Technology Sales RTS7751R2D support 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Board specific addresses. */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define PA_BCR 0xa4000000 /* FPGA */ 16*4882a593Smuzhiyun #define PA_IRLMON 0xa4000002 /* Interrupt Status control */ 17*4882a593Smuzhiyun #define PA_CFCTL 0xa4000004 /* CF Timing control */ 18*4882a593Smuzhiyun #define PA_CFPOW 0xa4000006 /* CF Power control */ 19*4882a593Smuzhiyun #define PA_DISPCTL 0xa4000008 /* Display Timing control */ 20*4882a593Smuzhiyun #define PA_SDMPOW 0xa400000a /* SD Power control */ 21*4882a593Smuzhiyun #define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */ 22*4882a593Smuzhiyun #define PA_PCICD 0xa400000e /* PCI Extension detect control */ 23*4882a593Smuzhiyun #define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */ 26*4882a593Smuzhiyun #define PA_R2D1_CFRST 0xa4000024 /* CF Reset control */ 27*4882a593Smuzhiyun #define PA_R2D1_ADMRTS 0xa4000026 /* SD Reset control */ 28*4882a593Smuzhiyun #define PA_R2D1_EXTRST 0xa4000028 /* Extension Reset control */ 29*4882a593Smuzhiyun #define PA_R2D1_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define PA_R2DPLUS_CFRST 0xa4000022 /* CF Reset control */ 32*4882a593Smuzhiyun #define PA_R2DPLUS_ADMRTS 0xa4000024 /* SD Reset control */ 33*4882a593Smuzhiyun #define PA_R2DPLUS_EXTRST 0xa4000026 /* Extension Reset control */ 34*4882a593Smuzhiyun #define PA_R2DPLUS_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */ 35*4882a593Smuzhiyun #define PA_R2DPLUS_KEYCTLCLR 0xa400002a /* Key Interrupt clear */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define PA_POWOFF 0xa4000030 /* Board Power OFF control */ 38*4882a593Smuzhiyun #define PA_VERREG 0xa4000032 /* FPGA Version Register */ 39*4882a593Smuzhiyun #define PA_INPORT 0xa4000034 /* KEY Input Port control */ 40*4882a593Smuzhiyun #define PA_OUTPORT 0xa4000036 /* LED control */ 41*4882a593Smuzhiyun #define PA_BVERREG 0xa4000038 /* Board Revision Register */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define PA_AX88796L 0xaa000400 /* AX88796L Area */ 44*4882a593Smuzhiyun #define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */ 45*4882a593Smuzhiyun #define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ 46*4882a593Smuzhiyun #define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define R2D_FPGA_IRQ_BASE 100 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define IRQ_VOYAGER (R2D_FPGA_IRQ_BASE + 0) 53*4882a593Smuzhiyun #define IRQ_EXT (R2D_FPGA_IRQ_BASE + 1) 54*4882a593Smuzhiyun #define IRQ_TP (R2D_FPGA_IRQ_BASE + 2) 55*4882a593Smuzhiyun #define IRQ_RTC_T (R2D_FPGA_IRQ_BASE + 3) 56*4882a593Smuzhiyun #define IRQ_RTC_A (R2D_FPGA_IRQ_BASE + 4) 57*4882a593Smuzhiyun #define IRQ_SDCARD (R2D_FPGA_IRQ_BASE + 5) 58*4882a593Smuzhiyun #define IRQ_CF_CD (R2D_FPGA_IRQ_BASE + 6) 59*4882a593Smuzhiyun #define IRQ_CF_IDE (R2D_FPGA_IRQ_BASE + 7) 60*4882a593Smuzhiyun #define IRQ_AX88796 (R2D_FPGA_IRQ_BASE + 8) 61*4882a593Smuzhiyun #define IRQ_KEY (R2D_FPGA_IRQ_BASE + 9) 62*4882a593Smuzhiyun #define IRQ_PCI_INTA (R2D_FPGA_IRQ_BASE + 10) 63*4882a593Smuzhiyun #define IRQ_PCI_INTB (R2D_FPGA_IRQ_BASE + 11) 64*4882a593Smuzhiyun #define IRQ_PCI_INTC (R2D_FPGA_IRQ_BASE + 12) 65*4882a593Smuzhiyun #define IRQ_PCI_INTD (R2D_FPGA_IRQ_BASE + 13) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* arch/sh/boards/renesas/rts7751r2d/irq.c */ 68*4882a593Smuzhiyun void init_rts7751r2d_IRQ(void); 69*4882a593Smuzhiyun int rts7751r2d_irq_demux(int); 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #endif /* __ASM_SH_RENESAS_RTS7751R2D */ 72