1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * include/asm-sh/magicpanelr2.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007 Markus Brunner, Mark Jonas 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * I/O addresses and bitmasks for Magic Panel Release 2 board 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_SH_MAGICPANELR2_H 11*4882a593Smuzhiyun #define __ASM_SH_MAGICPANELR2_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/gpio.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define __IO_PREFIX mpr2 16*4882a593Smuzhiyun #include <asm/io_generic.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg) 20*4882a593Smuzhiyun #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg) 21*4882a593Smuzhiyun #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg) 22*4882a593Smuzhiyun #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg) 23*4882a593Smuzhiyun #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg) 24*4882a593Smuzhiyun #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define PA_LED PORT_PADR /* LED */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* BSC */ 31*4882a593Smuzhiyun #define CMNCR 0xA4FD0000UL 32*4882a593Smuzhiyun #define CS0BCR 0xA4FD0004UL 33*4882a593Smuzhiyun #define CS2BCR 0xA4FD0008UL 34*4882a593Smuzhiyun #define CS3BCR 0xA4FD000CUL 35*4882a593Smuzhiyun #define CS4BCR 0xA4FD0010UL 36*4882a593Smuzhiyun #define CS5ABCR 0xA4FD0014UL 37*4882a593Smuzhiyun #define CS5BBCR 0xA4FD0018UL 38*4882a593Smuzhiyun #define CS6ABCR 0xA4FD001CUL 39*4882a593Smuzhiyun #define CS6BBCR 0xA4FD0020UL 40*4882a593Smuzhiyun #define CS0WCR 0xA4FD0024UL 41*4882a593Smuzhiyun #define CS2WCR 0xA4FD0028UL 42*4882a593Smuzhiyun #define CS3WCR 0xA4FD002CUL 43*4882a593Smuzhiyun #define CS4WCR 0xA4FD0030UL 44*4882a593Smuzhiyun #define CS5AWCR 0xA4FD0034UL 45*4882a593Smuzhiyun #define CS5BWCR 0xA4FD0038UL 46*4882a593Smuzhiyun #define CS6AWCR 0xA4FD003CUL 47*4882a593Smuzhiyun #define CS6BWCR 0xA4FD0040UL 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* usb */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define PORT_UTRCTL 0xA405012CUL 53*4882a593Smuzhiyun #define PORT_UCLKCR_W 0xA40A0008UL 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define INTC_ICR0 0xA414FEE0UL 56*4882a593Smuzhiyun #define INTC_ICR1 0xA4140010UL 57*4882a593Smuzhiyun #define INTC_ICR2 0xA4140012UL 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* MTD */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define MPR2_MTD_BOOTLOADER_SIZE 0x00060000UL 62*4882a593Smuzhiyun #define MPR2_MTD_KERNEL_SIZE 0x00200000UL 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* __ASM_SH_MAGICPANELR2_H */ 65