1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_RENESAS_R7780RP_H 3*4882a593Smuzhiyun #define __ASM_SH_RENESAS_R7780RP_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* Box specific addresses. */ 6*4882a593Smuzhiyun #define PA_NORFLASH_ADDR 0x00000000 7*4882a593Smuzhiyun #define PA_NORFLASH_SIZE 0x04000000 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #if defined(CONFIG_SH_R7780MP) 10*4882a593Smuzhiyun #define PA_BCR 0xa4000000 /* FPGA */ 11*4882a593Smuzhiyun #define PA_SDPOW (-1) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */ 14*4882a593Smuzhiyun #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */ 15*4882a593Smuzhiyun #define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */ 16*4882a593Smuzhiyun #define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */ 17*4882a593Smuzhiyun #define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */ 18*4882a593Smuzhiyun #define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */ 19*4882a593Smuzhiyun #define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */ 20*4882a593Smuzhiyun #define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */ 21*4882a593Smuzhiyun #define PA_PCICD (PA_BCR+0x0010) /* PCI Connector detect control */ 22*4882a593Smuzhiyun #define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */ 23*4882a593Smuzhiyun #define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */ 24*4882a593Smuzhiyun #define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */ 25*4882a593Smuzhiyun #define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */ 26*4882a593Smuzhiyun #define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */ 27*4882a593Smuzhiyun #define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */ 28*4882a593Smuzhiyun #define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */ 29*4882a593Smuzhiyun #define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */ 30*4882a593Smuzhiyun #define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */ 31*4882a593Smuzhiyun #define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */ 32*4882a593Smuzhiyun #define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */ 33*4882a593Smuzhiyun #define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */ 34*4882a593Smuzhiyun #define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */ 35*4882a593Smuzhiyun #define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */ 36*4882a593Smuzhiyun #define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */ 37*4882a593Smuzhiyun #define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */ 38*4882a593Smuzhiyun #define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */ 39*4882a593Smuzhiyun #define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */ 40*4882a593Smuzhiyun #define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */ 41*4882a593Smuzhiyun #define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */ 42*4882a593Smuzhiyun #define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */ 43*4882a593Smuzhiyun #define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */ 44*4882a593Smuzhiyun #define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */ 45*4882a593Smuzhiyun #define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */ 46*4882a593Smuzhiyun #define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */ 47*4882a593Smuzhiyun #define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */ 48*4882a593Smuzhiyun #define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */ 49*4882a593Smuzhiyun #define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */ 50*4882a593Smuzhiyun #define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */ 51*4882a593Smuzhiyun #define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */ 52*4882a593Smuzhiyun #define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */ 53*4882a593Smuzhiyun #define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */ 54*4882a593Smuzhiyun #define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */ 55*4882a593Smuzhiyun #define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */ 56*4882a593Smuzhiyun #define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */ 57*4882a593Smuzhiyun #define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */ 58*4882a593Smuzhiyun #define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */ 59*4882a593Smuzhiyun #define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */ 60*4882a593Smuzhiyun #define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */ 61*4882a593Smuzhiyun #define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */ 62*4882a593Smuzhiyun #define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */ 63*4882a593Smuzhiyun #define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */ 64*4882a593Smuzhiyun #define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */ 65*4882a593Smuzhiyun #define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */ 66*4882a593Smuzhiyun #define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */ 67*4882a593Smuzhiyun #define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */ 68*4882a593Smuzhiyun #define PA_POFF (PA_BCR+0x0800) /* System Power Off control */ 69*4882a593Smuzhiyun #define PA_PMR (PA_BCR+0x0900) /* */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ 72*4882a593Smuzhiyun #define IVDR_CK_ON 8 /* iVDR Clock ON */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #elif defined(CONFIG_SH_R7780RP) 75*4882a593Smuzhiyun #define PA_POFF (-1) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define PA_BCR 0xa5000000 /* FPGA */ 78*4882a593Smuzhiyun #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */ 79*4882a593Smuzhiyun #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */ 80*4882a593Smuzhiyun #define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */ 81*4882a593Smuzhiyun #define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */ 82*4882a593Smuzhiyun #define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */ 83*4882a593Smuzhiyun #define PA_PCICD (PA_BCR+0x000a) /* PCI Connector detect control */ 84*4882a593Smuzhiyun #define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */ 85*4882a593Smuzhiyun #define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */ 86*4882a593Smuzhiyun #define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */ 87*4882a593Smuzhiyun #define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */ 88*4882a593Smuzhiyun #define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */ 89*4882a593Smuzhiyun #define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */ 90*4882a593Smuzhiyun #define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */ 91*4882a593Smuzhiyun #define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */ 92*4882a593Smuzhiyun #define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */ 93*4882a593Smuzhiyun #define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */ 94*4882a593Smuzhiyun #define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */ 95*4882a593Smuzhiyun #define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */ 96*4882a593Smuzhiyun #define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */ 97*4882a593Smuzhiyun #define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */ 98*4882a593Smuzhiyun #define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */ 99*4882a593Smuzhiyun #define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */ 100*4882a593Smuzhiyun #define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */ 101*4882a593Smuzhiyun #define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */ 102*4882a593Smuzhiyun #define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */ 103*4882a593Smuzhiyun #define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */ 104*4882a593Smuzhiyun #define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */ 105*4882a593Smuzhiyun #define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */ 106*4882a593Smuzhiyun #define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */ 107*4882a593Smuzhiyun #define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */ 108*4882a593Smuzhiyun #define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */ 109*4882a593Smuzhiyun #define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */ 110*4882a593Smuzhiyun #define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */ 111*4882a593Smuzhiyun #define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */ 112*4882a593Smuzhiyun #define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */ 113*4882a593Smuzhiyun #define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */ 114*4882a593Smuzhiyun #define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */ 115*4882a593Smuzhiyun #define PA_SMSMADR (PA_BCR+0x0502) /* 2-wire Serial Slave control */ 116*4882a593Smuzhiyun #define PA_SMMR (PA_BCR+0x0504) /* 2-wire Serial Mode control */ 117*4882a593Smuzhiyun #define PA_SMSADR1 (PA_BCR+0x0506) /* 2-wire Serial Address1 control */ 118*4882a593Smuzhiyun #define PA_SMTRDR1 (PA_BCR+0x0546) /* 2-wire Serial Data1 control */ 119*4882a593Smuzhiyun #define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */ 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define PA_AX88796L 0xa5800400 /* AX88796L Area */ 122*4882a593Smuzhiyun #define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */ 123*4882a593Smuzhiyun #define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ 124*4882a593Smuzhiyun #define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define IVDR_CK_ON 8 /* iVDR Clock ON */ 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #elif defined(CONFIG_SH_R7785RP) 131*4882a593Smuzhiyun #define PA_BCR 0xa4000000 /* FPGA */ 132*4882a593Smuzhiyun #define PA_SDPOW (-1) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define PA_PCISCR (PA_BCR+0x0000) 135*4882a593Smuzhiyun #define PA_IRLPRA (PA_BCR+0x0002) 136*4882a593Smuzhiyun #define PA_IRLPRB (PA_BCR+0x0004) 137*4882a593Smuzhiyun #define PA_IRLPRC (PA_BCR+0x0006) 138*4882a593Smuzhiyun #define PA_IRLPRD (PA_BCR+0x0008) 139*4882a593Smuzhiyun #define IRLCNTR1 (PA_BCR+0x0010) 140*4882a593Smuzhiyun #define PA_IRLPRE (PA_BCR+0x000a) 141*4882a593Smuzhiyun #define PA_IRLPRF (PA_BCR+0x000c) 142*4882a593Smuzhiyun #define PA_EXIRLCR (PA_BCR+0x000e) 143*4882a593Smuzhiyun #define PA_IRLMCR1 (PA_BCR+0x0010) 144*4882a593Smuzhiyun #define PA_IRLMCR2 (PA_BCR+0x0012) 145*4882a593Smuzhiyun #define PA_IRLSSR1 (PA_BCR+0x0014) 146*4882a593Smuzhiyun #define PA_IRLSSR2 (PA_BCR+0x0016) 147*4882a593Smuzhiyun #define PA_CFTCR (PA_BCR+0x0100) 148*4882a593Smuzhiyun #define PA_CFPCR (PA_BCR+0x0102) 149*4882a593Smuzhiyun #define PA_PCICR (PA_BCR+0x0110) 150*4882a593Smuzhiyun #define PA_IVDRCTL (PA_BCR+0x0112) 151*4882a593Smuzhiyun #define PA_IVDRSR (PA_BCR+0x0114) 152*4882a593Smuzhiyun #define PA_PDRSTCR (PA_BCR+0x0116) 153*4882a593Smuzhiyun #define PA_POFF (PA_BCR+0x0120) 154*4882a593Smuzhiyun #define PA_LCDCR (PA_BCR+0x0130) 155*4882a593Smuzhiyun #define PA_TPCR (PA_BCR+0x0140) 156*4882a593Smuzhiyun #define PA_TPCKCR (PA_BCR+0x0142) 157*4882a593Smuzhiyun #define PA_TPRSTR (PA_BCR+0x0144) 158*4882a593Smuzhiyun #define PA_TPXPDR (PA_BCR+0x0146) 159*4882a593Smuzhiyun #define PA_TPYPDR (PA_BCR+0x0148) 160*4882a593Smuzhiyun #define PA_GPIOPFR (PA_BCR+0x0150) 161*4882a593Smuzhiyun #define PA_GPIODR (PA_BCR+0x0152) 162*4882a593Smuzhiyun #define PA_OBLED (PA_BCR+0x0154) 163*4882a593Smuzhiyun #define PA_SWSR (PA_BCR+0x0156) 164*4882a593Smuzhiyun #define PA_VERREG (PA_BCR+0x0158) 165*4882a593Smuzhiyun #define PA_SMCR (PA_BCR+0x0200) 166*4882a593Smuzhiyun #define PA_SMSMADR (PA_BCR+0x0202) 167*4882a593Smuzhiyun #define PA_SMMR (PA_BCR+0x0204) 168*4882a593Smuzhiyun #define PA_SMSADR1 (PA_BCR+0x0206) 169*4882a593Smuzhiyun #define PA_SMSADR32 (PA_BCR+0x0244) 170*4882a593Smuzhiyun #define PA_SMTRDR1 (PA_BCR+0x0246) 171*4882a593Smuzhiyun #define PA_SMTRDR16 (PA_BCR+0x0264) 172*4882a593Smuzhiyun #define PA_CU3MDR (PA_BCR+0x0300) 173*4882a593Smuzhiyun #define PA_CU5MDR (PA_BCR+0x0302) 174*4882a593Smuzhiyun #define PA_MMSR (PA_BCR+0x0400) 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define IVDR_CK_ON 4 /* iVDR Clock ON */ 177*4882a593Smuzhiyun #endif 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #define HL_FPGA_IRQ_BASE 200 180*4882a593Smuzhiyun #define HL_NR_IRL 15 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun #define IRQ_AX88796 (HL_FPGA_IRQ_BASE + 0) 183*4882a593Smuzhiyun #define IRQ_CF (HL_FPGA_IRQ_BASE + 1) 184*4882a593Smuzhiyun #define IRQ_PSW (HL_FPGA_IRQ_BASE + 2) 185*4882a593Smuzhiyun #define IRQ_EXT0 (HL_FPGA_IRQ_BASE + 3) 186*4882a593Smuzhiyun #define IRQ_EXT1 (HL_FPGA_IRQ_BASE + 4) 187*4882a593Smuzhiyun #define IRQ_EXT2 (HL_FPGA_IRQ_BASE + 5) 188*4882a593Smuzhiyun #define IRQ_EXT3 (HL_FPGA_IRQ_BASE + 6) 189*4882a593Smuzhiyun #define IRQ_EXT4 (HL_FPGA_IRQ_BASE + 7) 190*4882a593Smuzhiyun #define IRQ_EXT5 (HL_FPGA_IRQ_BASE + 8) 191*4882a593Smuzhiyun #define IRQ_EXT6 (HL_FPGA_IRQ_BASE + 9) 192*4882a593Smuzhiyun #define IRQ_EXT7 (HL_FPGA_IRQ_BASE + 10) 193*4882a593Smuzhiyun #define IRQ_SMBUS (HL_FPGA_IRQ_BASE + 11) 194*4882a593Smuzhiyun #define IRQ_TP (HL_FPGA_IRQ_BASE + 12) 195*4882a593Smuzhiyun #define IRQ_RTC (HL_FPGA_IRQ_BASE + 13) 196*4882a593Smuzhiyun #define IRQ_TH_ALERT (HL_FPGA_IRQ_BASE + 14) 197*4882a593Smuzhiyun #define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15) 198*4882a593Smuzhiyun #define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16) 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun unsigned char *highlander_plat_irq_setup(void); 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun #ifdef CONFIG_SH_R7785RP 203*4882a593Smuzhiyun void highlander_plat_pinmux_setup(void); 204*4882a593Smuzhiyun #else 205*4882a593Smuzhiyun #define highlander_plat_pinmux_setup() do { } while (0) 206*4882a593Smuzhiyun #endif 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #endif /* __ASM_SH_RENESAS_R7780RP */ 209