1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * include/asm-sh/cpu-sh4/watchdog.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2002, 2003 Paul Mundt 6*4882a593Smuzhiyun * Copyright (C) 2009 Siemens AG 7*4882a593Smuzhiyun * Copyright (C) 2009 Sitdikov Valentin 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __ASM_CPU_SH4_WATCHDOG_H 10*4882a593Smuzhiyun #define __ASM_CPU_SH4_WATCHDOG_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7780) 13*4882a593Smuzhiyun /* Prefix definition */ 14*4882a593Smuzhiyun #define WTBST_HIGH 0x55 15*4882a593Smuzhiyun /* Register definitions */ 16*4882a593Smuzhiyun #define WTCNT_R 0xffcc0010 /*WDTCNT*/ 17*4882a593Smuzhiyun #define WTCSR 0xffcc0004 /*WDTCSR*/ 18*4882a593Smuzhiyun #define WTCNT 0xffcc0000 /*WDTST*/ 19*4882a593Smuzhiyun #define WTST WTCNT 20*4882a593Smuzhiyun #define WTBST 0xffcc0008 /*WDTBST*/ 21*4882a593Smuzhiyun /* Register definitions */ 22*4882a593Smuzhiyun #elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \ 23*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7723) || \ 24*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7724) 25*4882a593Smuzhiyun #define WTCNT 0xa4520000 26*4882a593Smuzhiyun #define WTCSR 0xa4520004 27*4882a593Smuzhiyun #else 28*4882a593Smuzhiyun /* Register definitions */ 29*4882a593Smuzhiyun #define WTCNT 0xffc00008 30*4882a593Smuzhiyun #define WTCSR 0xffc0000c 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Bit definitions */ 34*4882a593Smuzhiyun #define WTCSR_TME 0x80 35*4882a593Smuzhiyun #define WTCSR_WT 0x40 36*4882a593Smuzhiyun #define WTCSR_RSTS 0x20 37*4882a593Smuzhiyun #define WTCSR_WOVF 0x10 38*4882a593Smuzhiyun #define WTCSR_IOVF 0x08 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif /* __ASM_CPU_SH4_WATCHDOG_H */ 41*4882a593Smuzhiyun 42