1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * include/asm-sh/cpu-sh4/mmu_context.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1999 Niibe Yutaka 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __ASM_CPU_SH4_MMU_CONTEXT_H 8*4882a593Smuzhiyun #define __ASM_CPU_SH4_MMU_CONTEXT_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */ 11*4882a593Smuzhiyun #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ 12*4882a593Smuzhiyun #define MMU_TTB 0xFF000008 /* Translation table base register */ 13*4882a593Smuzhiyun #define MMU_TEA 0xFF00000C /* TLB Exception Address */ 14*4882a593Smuzhiyun #define MMU_PTEA 0xFF000034 /* PTE assistance register */ 15*4882a593Smuzhiyun #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define MMUCR 0xFF000010 /* MMU Control Register */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MMU_TLB_ENTRY_SHIFT 8 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000 22*4882a593Smuzhiyun #define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000 23*4882a593Smuzhiyun #define MMU_ITLB_DATA_ARRAY 0xF3000000 24*4882a593Smuzhiyun #define MMU_ITLB_DATA_ARRAY2 0xF3800000 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 27*4882a593Smuzhiyun #define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000 28*4882a593Smuzhiyun #define MMU_UTLB_DATA_ARRAY 0xF7000000 29*4882a593Smuzhiyun #define MMU_UTLB_DATA_ARRAY2 0xF7800000 30*4882a593Smuzhiyun #define MMU_PAGE_ASSOC_BIT 0x80 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifdef CONFIG_MMU 33*4882a593Smuzhiyun #define MMUCR_AT (1 << 0) 34*4882a593Smuzhiyun #else 35*4882a593Smuzhiyun #define MMUCR_AT (0) 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define MMUCR_TI (1 << 2) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define MMUCR_URB 0x00FC0000 41*4882a593Smuzhiyun #define MMUCR_URB_SHIFT 18 42*4882a593Smuzhiyun #define MMUCR_URB_NENTRIES 64 43*4882a593Smuzhiyun #define MMUCR_URC 0x0000FC00 44*4882a593Smuzhiyun #define MMUCR_URC_SHIFT 10 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40) 47*4882a593Smuzhiyun #define MMUCR_SE (1 << 4) 48*4882a593Smuzhiyun #else 49*4882a593Smuzhiyun #define MMUCR_SE (0) 50*4882a593Smuzhiyun #endif 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #ifdef CONFIG_CPU_HAS_PTEAEX 53*4882a593Smuzhiyun #define MMUCR_AEX (1 << 6) 54*4882a593Smuzhiyun #else 55*4882a593Smuzhiyun #define MMUCR_AEX (0) 56*4882a593Smuzhiyun #endif 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #ifdef CONFIG_X2TLB 59*4882a593Smuzhiyun #define MMUCR_ME (1 << 7) 60*4882a593Smuzhiyun #else 61*4882a593Smuzhiyun #define MMUCR_ME (0) 62*4882a593Smuzhiyun #endif 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #ifdef CONFIG_SH_STORE_QUEUES 65*4882a593Smuzhiyun #define MMUCR_SQMD (1 << 9) 66*4882a593Smuzhiyun #else 67*4882a593Smuzhiyun #define MMUCR_SQMD (0) 68*4882a593Smuzhiyun #endif 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define MMU_NTLB_ENTRIES 64 71*4882a593Smuzhiyun #define MMU_CONTROL_INIT (MMUCR_AT | MMUCR_TI | MMUCR_SQMD | \ 72*4882a593Smuzhiyun MMUCR_ME | MMUCR_SE | MMUCR_AEX) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define TRA 0xff000020 75*4882a593Smuzhiyun #define EXPEVT 0xff000024 76*4882a593Smuzhiyun #define INTEVT 0xff000028 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */ 79*4882a593Smuzhiyun 80