1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * include/asm-sh/cpu-sh4/freq.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2002, 2003 Paul Mundt 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __ASM_CPU_SH4_FREQ_H 8*4882a593Smuzhiyun #define __ASM_CPU_SH4_FREQ_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7722) || \ 11*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7723) || \ 12*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7343) || \ 13*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7366) 14*4882a593Smuzhiyun #define FRQCR 0xa4150000 15*4882a593Smuzhiyun #define VCLKCR 0xa4150004 16*4882a593Smuzhiyun #define SCLKACR 0xa4150008 17*4882a593Smuzhiyun #define SCLKBCR 0xa415000c 18*4882a593Smuzhiyun #define IrDACLKCR 0xa4150010 19*4882a593Smuzhiyun #define MSTPCR0 0xa4150030 20*4882a593Smuzhiyun #define MSTPCR1 0xa4150034 21*4882a593Smuzhiyun #define MSTPCR2 0xa4150038 22*4882a593Smuzhiyun #elif defined(CONFIG_CPU_SUBTYPE_SH7757) 23*4882a593Smuzhiyun #define FRQCR 0xffc80000 24*4882a593Smuzhiyun #define OSCCR 0xffc80018 25*4882a593Smuzhiyun #define PLLCR 0xffc80024 26*4882a593Smuzhiyun #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 27*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7780) 28*4882a593Smuzhiyun #define FRQCR 0xffc80000 29*4882a593Smuzhiyun #elif defined(CONFIG_CPU_SUBTYPE_SH7724) 30*4882a593Smuzhiyun #define FRQCRA 0xa4150000 31*4882a593Smuzhiyun #define FRQCRB 0xa4150004 32*4882a593Smuzhiyun #define VCLKCR 0xa4150048 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define FCLKACR 0xa4150008 35*4882a593Smuzhiyun #define FCLKBCR 0xa415000c 36*4882a593Smuzhiyun #define FRQCR FRQCRA 37*4882a593Smuzhiyun #define SCLKACR FCLKACR 38*4882a593Smuzhiyun #define SCLKBCR FCLKBCR 39*4882a593Smuzhiyun #define FCLKACR 0xa4150008 40*4882a593Smuzhiyun #define FCLKBCR 0xa415000c 41*4882a593Smuzhiyun #define IrDACLKCR 0xa4150018 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define MSTPCR0 0xa4150030 44*4882a593Smuzhiyun #define MSTPCR1 0xa4150034 45*4882a593Smuzhiyun #define MSTPCR2 0xa4150038 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #elif defined(CONFIG_CPU_SUBTYPE_SH7734) 48*4882a593Smuzhiyun #define FRQCR0 0xffc80000 49*4882a593Smuzhiyun #define FRQCR2 0xffc80008 50*4882a593Smuzhiyun #define FRQMR1 0xffc80014 51*4882a593Smuzhiyun #define FRQMR2 0xffc80018 52*4882a593Smuzhiyun #elif defined(CONFIG_CPU_SUBTYPE_SH7785) 53*4882a593Smuzhiyun #define FRQCR0 0xffc80000 54*4882a593Smuzhiyun #define FRQCR1 0xffc80004 55*4882a593Smuzhiyun #define FRQMR1 0xffc80014 56*4882a593Smuzhiyun #elif defined(CONFIG_CPU_SUBTYPE_SH7786) 57*4882a593Smuzhiyun #define FRQCR0 0xffc40000 58*4882a593Smuzhiyun #define FRQCR1 0xffc40004 59*4882a593Smuzhiyun #define FRQMR1 0xffc40014 60*4882a593Smuzhiyun #elif defined(CONFIG_CPU_SUBTYPE_SHX3) 61*4882a593Smuzhiyun #define FRQCR0 0xffc00000 62*4882a593Smuzhiyun #define FRQCR1 0xffc00004 63*4882a593Smuzhiyun #define FRQMR1 0xffc00014 64*4882a593Smuzhiyun #else 65*4882a593Smuzhiyun #define FRQCR 0xffc00000 66*4882a593Smuzhiyun #define FRQCR_PSTBY 0x0200 67*4882a593Smuzhiyun #define FRQCR_PLLEN 0x0400 68*4882a593Smuzhiyun #define FRQCR_CKOEN 0x0800 69*4882a593Smuzhiyun #endif 70*4882a593Smuzhiyun #define MIN_DIVISOR_NR 0 71*4882a593Smuzhiyun #define MAX_DIVISOR_NR 3 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* __ASM_CPU_SH4_FREQ_H */ 74*4882a593Smuzhiyun 75