1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * linux/arch/sh/kernel/cpu/sh4/sh4_fpu.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2006 STMicroelectronics Limited 6*4882a593Smuzhiyun * Author: Carl Shaw <carl.shaw@st.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Definitions for SH4 FPU operations 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __CPU_SH4_FPU_H 12*4882a593Smuzhiyun #define __CPU_SH4_FPU_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define FPSCR_ENABLE_MASK 0x00000f80UL 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define FPSCR_FMOV_DOUBLE (1<<1) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define FPSCR_CAUSE_INEXACT (1<<12) 19*4882a593Smuzhiyun #define FPSCR_CAUSE_UNDERFLOW (1<<13) 20*4882a593Smuzhiyun #define FPSCR_CAUSE_OVERFLOW (1<<14) 21*4882a593Smuzhiyun #define FPSCR_CAUSE_DIVZERO (1<<15) 22*4882a593Smuzhiyun #define FPSCR_CAUSE_INVALID (1<<16) 23*4882a593Smuzhiyun #define FPSCR_CAUSE_ERROR (1<<17) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define FPSCR_DBL_PRECISION (1<<19) 26*4882a593Smuzhiyun #define FPSCR_ROUNDING_MODE(x) ((x >> 20) & 3) 27*4882a593Smuzhiyun #define FPSCR_RM_NEAREST (0) 28*4882a593Smuzhiyun #define FPSCR_RM_ZERO (1) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #endif 31