1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * SH4 CPU-specific DMA definitions, used by both DMA drivers 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef CPU_DMA_REGISTER_H 8*4882a593Smuzhiyun #define CPU_DMA_REGISTER_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* SH7751/7760/7780 DMA IRQ sources */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifdef CONFIG_CPU_SH4A 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define DMAOR_INIT DMAOR_DME 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7343) 17*4882a593Smuzhiyun #define CHCR_TS_LOW_MASK 0x00000018 18*4882a593Smuzhiyun #define CHCR_TS_LOW_SHIFT 3 19*4882a593Smuzhiyun #define CHCR_TS_HIGH_MASK 0 20*4882a593Smuzhiyun #define CHCR_TS_HIGH_SHIFT 0 21*4882a593Smuzhiyun #elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \ 22*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7723) || \ 23*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7724) || \ 24*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7730) || \ 25*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7786) 26*4882a593Smuzhiyun #define CHCR_TS_LOW_MASK 0x00000018 27*4882a593Smuzhiyun #define CHCR_TS_LOW_SHIFT 3 28*4882a593Smuzhiyun #define CHCR_TS_HIGH_MASK 0x00300000 29*4882a593Smuzhiyun #define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ 30*4882a593Smuzhiyun #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \ 31*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 32*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 33*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7785) 34*4882a593Smuzhiyun #define CHCR_TS_LOW_MASK 0x00000018 35*4882a593Smuzhiyun #define CHCR_TS_LOW_SHIFT 3 36*4882a593Smuzhiyun #define CHCR_TS_HIGH_MASK 0x00100000 37*4882a593Smuzhiyun #define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ 38*4882a593Smuzhiyun #endif 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Transmit sizes and respective CHCR register values */ 41*4882a593Smuzhiyun enum { 42*4882a593Smuzhiyun XMIT_SZ_8BIT = 0, 43*4882a593Smuzhiyun XMIT_SZ_16BIT = 1, 44*4882a593Smuzhiyun XMIT_SZ_32BIT = 2, 45*4882a593Smuzhiyun XMIT_SZ_64BIT = 7, 46*4882a593Smuzhiyun XMIT_SZ_128BIT = 3, 47*4882a593Smuzhiyun XMIT_SZ_256BIT = 4, 48*4882a593Smuzhiyun XMIT_SZ_128BIT_BLK = 0xb, 49*4882a593Smuzhiyun XMIT_SZ_256BIT_BLK = 0xc, 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* log2(size / 8) - used to calculate number of transfers */ 53*4882a593Smuzhiyun #define TS_SHIFT { \ 54*4882a593Smuzhiyun [XMIT_SZ_8BIT] = 0, \ 55*4882a593Smuzhiyun [XMIT_SZ_16BIT] = 1, \ 56*4882a593Smuzhiyun [XMIT_SZ_32BIT] = 2, \ 57*4882a593Smuzhiyun [XMIT_SZ_64BIT] = 3, \ 58*4882a593Smuzhiyun [XMIT_SZ_128BIT] = 4, \ 59*4882a593Smuzhiyun [XMIT_SZ_256BIT] = 5, \ 60*4882a593Smuzhiyun [XMIT_SZ_128BIT_BLK] = 4, \ 61*4882a593Smuzhiyun [XMIT_SZ_256BIT_BLK] = 5, \ 62*4882a593Smuzhiyun } 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \ 65*4882a593Smuzhiyun (((i) & 0xc) << CHCR_TS_HIGH_SHIFT)) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #else /* CONFIG_CPU_SH4A */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define DMAOR_INIT (0x8000 | DMAOR_DME) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define CHCR_TS_LOW_MASK 0x70 72*4882a593Smuzhiyun #define CHCR_TS_LOW_SHIFT 4 73*4882a593Smuzhiyun #define CHCR_TS_HIGH_MASK 0 74*4882a593Smuzhiyun #define CHCR_TS_HIGH_SHIFT 0 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Transmit sizes and respective CHCR register values */ 77*4882a593Smuzhiyun enum { 78*4882a593Smuzhiyun XMIT_SZ_8BIT = 1, 79*4882a593Smuzhiyun XMIT_SZ_16BIT = 2, 80*4882a593Smuzhiyun XMIT_SZ_32BIT = 3, 81*4882a593Smuzhiyun XMIT_SZ_64BIT = 0, 82*4882a593Smuzhiyun XMIT_SZ_256BIT = 4, 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* log2(size / 8) - used to calculate number of transfers */ 86*4882a593Smuzhiyun #define TS_SHIFT { \ 87*4882a593Smuzhiyun [XMIT_SZ_8BIT] = 0, \ 88*4882a593Smuzhiyun [XMIT_SZ_16BIT] = 1, \ 89*4882a593Smuzhiyun [XMIT_SZ_32BIT] = 2, \ 90*4882a593Smuzhiyun [XMIT_SZ_64BIT] = 3, \ 91*4882a593Smuzhiyun [XMIT_SZ_256BIT] = 5, \ 92*4882a593Smuzhiyun } 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #endif /* CONFIG_CPU_SH4A */ 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #endif 99