1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 1999 by Kaz Kojima 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Defitions for the address spaces of the SH-4 CPUs. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __ASM_CPU_SH4_ADDRSPACE_H 8*4882a593Smuzhiyun #define __ASM_CPU_SH4_ADDRSPACE_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define P0SEG 0x00000000 11*4882a593Smuzhiyun #define P1SEG 0x80000000 12*4882a593Smuzhiyun #define P2SEG 0xa0000000 13*4882a593Smuzhiyun #define P3SEG 0xc0000000 14*4882a593Smuzhiyun #define P4SEG 0xe0000000 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Detailed P4SEG */ 17*4882a593Smuzhiyun #define P4SEG_STORE_QUE (P4SEG) 18*4882a593Smuzhiyun #define P4SEG_IC_ADDR 0xf0000000 19*4882a593Smuzhiyun #define P4SEG_IC_DATA 0xf1000000 20*4882a593Smuzhiyun #define P4SEG_ITLB_ADDR 0xf2000000 21*4882a593Smuzhiyun #define P4SEG_ITLB_DATA 0xf3000000 22*4882a593Smuzhiyun #define P4SEG_OC_ADDR 0xf4000000 23*4882a593Smuzhiyun #define P4SEG_OC_DATA 0xf5000000 24*4882a593Smuzhiyun #define P4SEG_TLB_ADDR 0xf6000000 25*4882a593Smuzhiyun #define P4SEG_TLB_DATA 0xf7000000 26*4882a593Smuzhiyun #define P4SEG_REG_BASE 0xff000000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define PA_AREA0 0x00000000 29*4882a593Smuzhiyun #define PA_AREA1 0x04000000 30*4882a593Smuzhiyun #define PA_AREA2 0x08000000 31*4882a593Smuzhiyun #define PA_AREA3 0x0c000000 32*4882a593Smuzhiyun #define PA_AREA4 0x10000000 33*4882a593Smuzhiyun #define PA_AREA5 0x14000000 34*4882a593Smuzhiyun #define PA_AREA6 0x18000000 35*4882a593Smuzhiyun #define PA_AREA7 0x1c000000 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */ 38*4882a593Smuzhiyun #define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif /* __ASM_CPU_SH4_ADDRSPACE_H */ 41*4882a593Smuzhiyun 42