1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * include/asm-sh/cpu-sh3/mmu_context.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1999 Niibe Yutaka 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __ASM_CPU_SH3_MMU_CONTEXT_H 8*4882a593Smuzhiyun #define __ASM_CPU_SH3_MMU_CONTEXT_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */ 11*4882a593Smuzhiyun #define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */ 12*4882a593Smuzhiyun #define MMU_TTB 0xFFFFFFF8 /* Translation table base register */ 13*4882a593Smuzhiyun #define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define MMUCR 0xFFFFFFE0 /* MMU Control Register */ 16*4882a593Smuzhiyun #define MMUCR_TI (1 << 2) /* TLB flush bit */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define MMU_TLB_ADDRESS_ARRAY 0xF2000000 19*4882a593Smuzhiyun #define MMU_PAGE_ASSOC_BIT 0x80 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define MMU_NTLB_ENTRIES 128 /* for 7708 */ 22*4882a593Smuzhiyun #define MMU_NTLB_WAYS 4 23*4882a593Smuzhiyun #define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define TRA 0xffffffd0 26*4882a593Smuzhiyun #define EXPEVT 0xffffffd4 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 29*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 30*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 31*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 32*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 33*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7712) || \ 34*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 35*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7721) 36*4882a593Smuzhiyun #define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ 37*4882a593Smuzhiyun #else 38*4882a593Smuzhiyun #define INTEVT 0xffffffd8 39*4882a593Smuzhiyun #endif 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */ 42*4882a593Smuzhiyun 43