1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * include/asm-sh/cpu-sh3/gpio.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007 Markus Brunner, Mark Jonas 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Addresses for the Pin Function Controller 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef _CPU_SH3_GPIO_H 10*4882a593Smuzhiyun #define _CPU_SH3_GPIO_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 13*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7721) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Control registers */ 16*4882a593Smuzhiyun #define PORT_PACR 0xA4050100UL 17*4882a593Smuzhiyun #define PORT_PBCR 0xA4050102UL 18*4882a593Smuzhiyun #define PORT_PCCR 0xA4050104UL 19*4882a593Smuzhiyun #define PORT_PDCR 0xA4050106UL 20*4882a593Smuzhiyun #define PORT_PECR 0xA4050108UL 21*4882a593Smuzhiyun #define PORT_PFCR 0xA405010AUL 22*4882a593Smuzhiyun #define PORT_PGCR 0xA405010CUL 23*4882a593Smuzhiyun #define PORT_PHCR 0xA405010EUL 24*4882a593Smuzhiyun #define PORT_PJCR 0xA4050110UL 25*4882a593Smuzhiyun #define PORT_PKCR 0xA4050112UL 26*4882a593Smuzhiyun #define PORT_PLCR 0xA4050114UL 27*4882a593Smuzhiyun #define PORT_PMCR 0xA4050116UL 28*4882a593Smuzhiyun #define PORT_PPCR 0xA4050118UL 29*4882a593Smuzhiyun #define PORT_PRCR 0xA405011AUL 30*4882a593Smuzhiyun #define PORT_PSCR 0xA405011CUL 31*4882a593Smuzhiyun #define PORT_PTCR 0xA405011EUL 32*4882a593Smuzhiyun #define PORT_PUCR 0xA4050120UL 33*4882a593Smuzhiyun #define PORT_PVCR 0xA4050122UL 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Data registers */ 36*4882a593Smuzhiyun #define PORT_PADR 0xA4050140UL 37*4882a593Smuzhiyun /* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */ 38*4882a593Smuzhiyun #define PORT_PBDR 0xA4050142UL 39*4882a593Smuzhiyun #define PORT_PCDR 0xA4050144UL 40*4882a593Smuzhiyun #define PORT_PDDR 0xA4050146UL 41*4882a593Smuzhiyun #define PORT_PEDR 0xA4050148UL 42*4882a593Smuzhiyun #define PORT_PFDR 0xA405014AUL 43*4882a593Smuzhiyun #define PORT_PGDR 0xA405014CUL 44*4882a593Smuzhiyun #define PORT_PHDR 0xA405014EUL 45*4882a593Smuzhiyun #define PORT_PJDR 0xA4050150UL 46*4882a593Smuzhiyun #define PORT_PKDR 0xA4050152UL 47*4882a593Smuzhiyun #define PORT_PLDR 0xA4050154UL 48*4882a593Smuzhiyun #define PORT_PMDR 0xA4050156UL 49*4882a593Smuzhiyun #define PORT_PPDR 0xA4050158UL 50*4882a593Smuzhiyun #define PORT_PRDR 0xA405015AUL 51*4882a593Smuzhiyun #define PORT_PSDR 0xA405015CUL 52*4882a593Smuzhiyun #define PORT_PTDR 0xA405015EUL 53*4882a593Smuzhiyun #define PORT_PUDR 0xA4050160UL 54*4882a593Smuzhiyun #define PORT_PVDR 0xA4050162UL 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Pin Select Registers */ 57*4882a593Smuzhiyun #define PORT_PSELA 0xA4050124UL 58*4882a593Smuzhiyun #define PORT_PSELB 0xA4050126UL 59*4882a593Smuzhiyun #define PORT_PSELC 0xA4050128UL 60*4882a593Smuzhiyun #define PORT_PSELD 0xA405012AUL 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #elif defined(CONFIG_CPU_SUBTYPE_SH7709) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Control registers */ 65*4882a593Smuzhiyun #define PORT_PACR 0xa4000100UL 66*4882a593Smuzhiyun #define PORT_PBCR 0xa4000102UL 67*4882a593Smuzhiyun #define PORT_PCCR 0xa4000104UL 68*4882a593Smuzhiyun #define PORT_PFCR 0xa400010aUL 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Data registers */ 71*4882a593Smuzhiyun #define PORT_PADR 0xa4000120UL 72*4882a593Smuzhiyun #define PORT_PBDR 0xa4000122UL 73*4882a593Smuzhiyun #define PORT_PCDR 0xa4000124UL 74*4882a593Smuzhiyun #define PORT_PFDR 0xa400012aUL 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #endif 79