1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * SH3 CPU-specific DMA definitions, used by both DMA drivers 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef CPU_DMA_REGISTER_H 8*4882a593Smuzhiyun #define CPU_DMA_REGISTER_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CHCR_TS_LOW_MASK 0x18 11*4882a593Smuzhiyun #define CHCR_TS_LOW_SHIFT 3 12*4882a593Smuzhiyun #define CHCR_TS_HIGH_MASK 0 13*4882a593Smuzhiyun #define CHCR_TS_HIGH_SHIFT 0 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define DMAOR_INIT DMAOR_DME 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * The SuperH DMAC supports a number of transmit sizes, we list them here, 19*4882a593Smuzhiyun * with their respective values as they appear in the CHCR registers. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun enum { 22*4882a593Smuzhiyun XMIT_SZ_8BIT, 23*4882a593Smuzhiyun XMIT_SZ_16BIT, 24*4882a593Smuzhiyun XMIT_SZ_32BIT, 25*4882a593Smuzhiyun XMIT_SZ_128BIT, 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* log2(size / 8) - used to calculate number of transfers */ 29*4882a593Smuzhiyun #define TS_SHIFT { \ 30*4882a593Smuzhiyun [XMIT_SZ_8BIT] = 0, \ 31*4882a593Smuzhiyun [XMIT_SZ_16BIT] = 1, \ 32*4882a593Smuzhiyun [XMIT_SZ_32BIT] = 2, \ 33*4882a593Smuzhiyun [XMIT_SZ_128BIT] = 4, \ 34*4882a593Smuzhiyun } 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #endif 39