1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * include/asm-sh/cpu-sh3/cache.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1999 Niibe Yutaka 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __ASM_CPU_SH3_CACHE_H 8*4882a593Smuzhiyun #define __ASM_CPU_SH3_CACHE_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define L1_CACHE_SHIFT 4 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define SH_CACHE_VALID 1 13*4882a593Smuzhiyun #define SH_CACHE_UPDATED 2 14*4882a593Smuzhiyun #define SH_CACHE_COMBINED 4 15*4882a593Smuzhiyun #define SH_CACHE_ASSOC 8 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define SH_CCR 0xffffffec /* Address of Cache Control Register */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CCR_CACHE_CE 0x01 /* Cache Enable */ 20*4882a593Smuzhiyun #define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */ 21*4882a593Smuzhiyun #define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */ 22*4882a593Smuzhiyun #define CCR_CACHE_CF 0x08 /* Cache Flush */ 23*4882a593Smuzhiyun #define CCR_CACHE_ORA 0x20 /* RAM mode */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define CACHE_OC_ADDRESS_ARRAY 0xf0000000 26*4882a593Smuzhiyun #define CACHE_PHYSADDR_MASK 0x1ffffc00 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define CCR_CACHE_ENABLE CCR_CACHE_CE 29*4882a593Smuzhiyun #define CCR_CACHE_INVALIDATE CCR_CACHE_CF 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 32*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 33*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 34*4882a593Smuzhiyun defined(CONFIG_CPU_SUBTYPE_SH7721) 35*4882a593Smuzhiyun #define CCR3_REG 0xa40000b4 36*4882a593Smuzhiyun #define CCR_CACHE_16KB 0x00010000 37*4882a593Smuzhiyun #define CCR_CACHE_32KB 0x00020000 38*4882a593Smuzhiyun #endif 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif /* __ASM_CPU_SH3_CACHE_H */ 41