1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * include/asm-sh/cpu-sh2/watchdog.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2002, 2003 Paul Mundt 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __ASM_CPU_SH2_WATCHDOG_H 8*4882a593Smuzhiyun #define __ASM_CPU_SH2_WATCHDOG_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * More SH-2 brilliance .. its not good enough that we can't read 12*4882a593Smuzhiyun * and write the same sizes to WTCNT, now we have to read and write 13*4882a593Smuzhiyun * with different sizes at different addresses for WTCNT _and_ RSTCSR. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * At least on the bright side no one has managed to screw over WTCSR 16*4882a593Smuzhiyun * in this fashion .. yet. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun /* Register definitions */ 19*4882a593Smuzhiyun #define WTCNT 0xfffffe80 20*4882a593Smuzhiyun #define WTCSR 0xfffffe80 21*4882a593Smuzhiyun #define RSTCSR 0xfffffe82 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define WTCNT_R (WTCNT + 1) 24*4882a593Smuzhiyun #define RSTCSR_R (RSTCSR + 1) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Bit definitions */ 27*4882a593Smuzhiyun #define WTCSR_IOVF 0x80 28*4882a593Smuzhiyun #define WTCSR_WT 0x40 29*4882a593Smuzhiyun #define WTCSR_TME 0x20 30*4882a593Smuzhiyun #define WTCSR_RSTS 0x00 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define RSTCSR_RSTS 0x20 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /** 35*4882a593Smuzhiyun * sh_wdt_read_rstcsr - Read from Reset Control/Status Register 36*4882a593Smuzhiyun * 37*4882a593Smuzhiyun * Reads back the RSTCSR value. 38*4882a593Smuzhiyun */ sh_wdt_read_rstcsr(void)39*4882a593Smuzhiyunstatic inline __u8 sh_wdt_read_rstcsr(void) 40*4882a593Smuzhiyun { 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * Same read/write brain-damage as for WTCNT here.. 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun return __raw_readb(RSTCSR_R); 45*4882a593Smuzhiyun } 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /** 48*4882a593Smuzhiyun * sh_wdt_write_csr - Write to Reset Control/Status Register 49*4882a593Smuzhiyun * 50*4882a593Smuzhiyun * @val: Value to write 51*4882a593Smuzhiyun * 52*4882a593Smuzhiyun * Writes the given value @val to the lower byte of the control/status 53*4882a593Smuzhiyun * register. The upper byte is set manually on each write. 54*4882a593Smuzhiyun */ sh_wdt_write_rstcsr(__u8 val)55*4882a593Smuzhiyunstatic inline void sh_wdt_write_rstcsr(__u8 val) 56*4882a593Smuzhiyun { 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * Note: Due to the brain-damaged nature of this register, 59*4882a593Smuzhiyun * we can't presently touch the WOVF bit, since the upper byte 60*4882a593Smuzhiyun * has to be swapped for this. So just leave it alone.. 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun __raw_writeb((WTCNT_HIGH << 8) | (__u16)val, RSTCSR); 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif /* __ASM_CPU_SH2_WATCHDOG_H */ 66*4882a593Smuzhiyun 67