1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_PROCESSOR_H 3*4882a593Smuzhiyun #define __ASM_SH_PROCESSOR_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <asm/cpu-features.h> 6*4882a593Smuzhiyun #include <asm/segment.h> 7*4882a593Smuzhiyun #include <asm/cache.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * CPU type and hardware bug flags. Kept separately for each CPU. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry 14*4882a593Smuzhiyun * in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c 15*4882a593Smuzhiyun * for parsing the subtype in get_cpu_subtype(). 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun enum cpu_type { 18*4882a593Smuzhiyun /* SH-2 types */ 19*4882a593Smuzhiyun CPU_SH7619, CPU_J2, 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* SH-2A types */ 22*4882a593Smuzhiyun CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269, 23*4882a593Smuzhiyun CPU_MXG, 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* SH-3 types */ 26*4882a593Smuzhiyun CPU_SH7705, CPU_SH7706, CPU_SH7707, 27*4882a593Smuzhiyun CPU_SH7708, CPU_SH7708S, CPU_SH7708R, 28*4882a593Smuzhiyun CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, 29*4882a593Smuzhiyun CPU_SH7720, CPU_SH7721, CPU_SH7729, 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* SH-4 types */ 32*4882a593Smuzhiyun CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, 33*4882a593Smuzhiyun CPU_SH7760, CPU_SH4_202, CPU_SH4_501, 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* SH-4A types */ 36*4882a593Smuzhiyun CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, 37*4882a593Smuzhiyun CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3, 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* SH4AL-DSP types */ 40*4882a593Smuzhiyun CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372, 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Unknown subtype */ 43*4882a593Smuzhiyun CPU_SH_NONE 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun enum cpu_family { 47*4882a593Smuzhiyun CPU_FAMILY_SH2, 48*4882a593Smuzhiyun CPU_FAMILY_SH2A, 49*4882a593Smuzhiyun CPU_FAMILY_SH3, 50*4882a593Smuzhiyun CPU_FAMILY_SH4, 51*4882a593Smuzhiyun CPU_FAMILY_SH4A, 52*4882a593Smuzhiyun CPU_FAMILY_SH4AL_DSP, 53*4882a593Smuzhiyun CPU_FAMILY_UNKNOWN, 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * TLB information structure 58*4882a593Smuzhiyun * 59*4882a593Smuzhiyun * Defined for both I and D tlb, per-processor. 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun struct tlb_info { 62*4882a593Smuzhiyun unsigned long long next; 63*4882a593Smuzhiyun unsigned long long first; 64*4882a593Smuzhiyun unsigned long long last; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun unsigned int entries; 67*4882a593Smuzhiyun unsigned int step; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun unsigned long flags; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun struct sh_cpuinfo { 73*4882a593Smuzhiyun unsigned int type, family; 74*4882a593Smuzhiyun int cut_major, cut_minor; 75*4882a593Smuzhiyun unsigned long loops_per_jiffy; 76*4882a593Smuzhiyun unsigned long asid_cache; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct cache_info icache; /* Primary I-cache */ 79*4882a593Smuzhiyun struct cache_info dcache; /* Primary D-cache */ 80*4882a593Smuzhiyun struct cache_info scache; /* Secondary cache */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* TLB info */ 83*4882a593Smuzhiyun struct tlb_info itlb; 84*4882a593Smuzhiyun struct tlb_info dtlb; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun unsigned int phys_bits; 87*4882a593Smuzhiyun unsigned long flags; 88*4882a593Smuzhiyun } __attribute__ ((aligned(L1_CACHE_BYTES))); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun extern struct sh_cpuinfo cpu_data[]; 91*4882a593Smuzhiyun #define boot_cpu_data cpu_data[0] 92*4882a593Smuzhiyun #define current_cpu_data cpu_data[smp_processor_id()] 93*4882a593Smuzhiyun #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory") 96*4882a593Smuzhiyun #define cpu_relax() barrier() 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun void default_idle(void); 99*4882a593Smuzhiyun void stop_this_cpu(void *); 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* Forward decl */ 102*4882a593Smuzhiyun struct seq_operations; 103*4882a593Smuzhiyun struct task_struct; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun extern struct pt_regs fake_swapper_regs; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun extern void cpu_init(void); 108*4882a593Smuzhiyun extern void cpu_probe(void); 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* arch/sh/kernel/process.c */ 111*4882a593Smuzhiyun extern unsigned int xstate_size; 112*4882a593Smuzhiyun extern void free_thread_xstate(struct task_struct *); 113*4882a593Smuzhiyun extern struct kmem_cache *task_xstate_cachep; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* arch/sh/mm/alignment.c */ 116*4882a593Smuzhiyun extern int get_unalign_ctl(struct task_struct *, unsigned long addr); 117*4882a593Smuzhiyun extern int set_unalign_ctl(struct task_struct *, unsigned int val); 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) 120*4882a593Smuzhiyun #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* arch/sh/mm/init.c */ 123*4882a593Smuzhiyun extern unsigned int mem_init_done; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* arch/sh/kernel/setup.c */ 126*4882a593Smuzhiyun const char *get_cpu_subtype(struct sh_cpuinfo *c); 127*4882a593Smuzhiyun extern const struct seq_operations cpuinfo_op; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* thread_struct flags */ 130*4882a593Smuzhiyun #define SH_THREAD_UAC_NOPRINT (1 << 0) 131*4882a593Smuzhiyun #define SH_THREAD_UAC_SIGBUS (1 << 1) 132*4882a593Smuzhiyun #define SH_THREAD_UAC_MASK (SH_THREAD_UAC_NOPRINT | SH_THREAD_UAC_SIGBUS) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* processor boot mode configuration */ 135*4882a593Smuzhiyun #define MODE_PIN0 (1 << 0) 136*4882a593Smuzhiyun #define MODE_PIN1 (1 << 1) 137*4882a593Smuzhiyun #define MODE_PIN2 (1 << 2) 138*4882a593Smuzhiyun #define MODE_PIN3 (1 << 3) 139*4882a593Smuzhiyun #define MODE_PIN4 (1 << 4) 140*4882a593Smuzhiyun #define MODE_PIN5 (1 << 5) 141*4882a593Smuzhiyun #define MODE_PIN6 (1 << 6) 142*4882a593Smuzhiyun #define MODE_PIN7 (1 << 7) 143*4882a593Smuzhiyun #define MODE_PIN8 (1 << 8) 144*4882a593Smuzhiyun #define MODE_PIN9 (1 << 9) 145*4882a593Smuzhiyun #define MODE_PIN10 (1 << 10) 146*4882a593Smuzhiyun #define MODE_PIN11 (1 << 11) 147*4882a593Smuzhiyun #define MODE_PIN12 (1 << 12) 148*4882a593Smuzhiyun #define MODE_PIN13 (1 << 13) 149*4882a593Smuzhiyun #define MODE_PIN14 (1 << 14) 150*4882a593Smuzhiyun #define MODE_PIN15 (1 << 15) 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun int generic_mode_pins(void); 153*4882a593Smuzhiyun int test_mode_pin(int pin); 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #ifdef CONFIG_VSYSCALL 156*4882a593Smuzhiyun int vsyscall_init(void); 157*4882a593Smuzhiyun #else 158*4882a593Smuzhiyun #define vsyscall_init() do { } while (0) 159*4882a593Smuzhiyun #endif 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* 162*4882a593Smuzhiyun * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks. 163*4882a593Smuzhiyun */ 164*4882a593Smuzhiyun #ifdef CONFIG_CPU_SH2A 165*4882a593Smuzhiyun extern unsigned int instruction_size(unsigned int insn); 166*4882a593Smuzhiyun #else 167*4882a593Smuzhiyun #define instruction_size(insn) (2) 168*4882a593Smuzhiyun #endif 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #include <asm/processor_32.h> 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #endif /* __ASM_SH_PROCESSOR_H */ 175