1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef __ASM_SH_PCI_H
3*4882a593Smuzhiyun #define __ASM_SH_PCI_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun /* Can be used to override the logic in pci_scan_bus for skipping
6*4882a593Smuzhiyun already-configured bus numbers - to be used for buggy BIOSes
7*4882a593Smuzhiyun or architectures with incomplete PCI setup by the loader */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #define pcibios_assign_all_busses() 1
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /*
12*4882a593Smuzhiyun * A board can define one or more PCI channels that represent built-in (or
13*4882a593Smuzhiyun * external) PCI controllers.
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun struct pci_channel {
16*4882a593Smuzhiyun struct pci_channel *next;
17*4882a593Smuzhiyun struct pci_bus *bus;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct pci_ops *pci_ops;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct resource *resources;
22*4882a593Smuzhiyun unsigned int nr_resources;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun unsigned long io_offset;
25*4882a593Smuzhiyun unsigned long mem_offset;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun unsigned long reg_base;
28*4882a593Smuzhiyun unsigned long io_map_base;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun unsigned int index;
31*4882a593Smuzhiyun unsigned int need_domain_info;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* Optional error handling */
34*4882a593Smuzhiyun struct timer_list err_timer, serr_timer;
35*4882a593Smuzhiyun unsigned int err_irq, serr_irq;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* arch/sh/drivers/pci/pci.c */
39*4882a593Smuzhiyun extern raw_spinlock_t pci_config_lock;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun extern int register_pci_controller(struct pci_channel *hose);
42*4882a593Smuzhiyun extern void pcibios_report_status(unsigned int status_mask, int warn);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* arch/sh/drivers/pci/common.c */
45*4882a593Smuzhiyun extern int early_read_config_byte(struct pci_channel *hose, int top_bus,
46*4882a593Smuzhiyun int bus, int devfn, int offset, u8 *value);
47*4882a593Smuzhiyun extern int early_read_config_word(struct pci_channel *hose, int top_bus,
48*4882a593Smuzhiyun int bus, int devfn, int offset, u16 *value);
49*4882a593Smuzhiyun extern int early_read_config_dword(struct pci_channel *hose, int top_bus,
50*4882a593Smuzhiyun int bus, int devfn, int offset, u32 *value);
51*4882a593Smuzhiyun extern int early_write_config_byte(struct pci_channel *hose, int top_bus,
52*4882a593Smuzhiyun int bus, int devfn, int offset, u8 value);
53*4882a593Smuzhiyun extern int early_write_config_word(struct pci_channel *hose, int top_bus,
54*4882a593Smuzhiyun int bus, int devfn, int offset, u16 value);
55*4882a593Smuzhiyun extern int early_write_config_dword(struct pci_channel *hose, int top_bus,
56*4882a593Smuzhiyun int bus, int devfn, int offset, u32 value);
57*4882a593Smuzhiyun extern void pcibios_enable_timers(struct pci_channel *hose);
58*4882a593Smuzhiyun extern unsigned int pcibios_handle_status_errors(unsigned long addr,
59*4882a593Smuzhiyun unsigned int status, struct pci_channel *hose);
60*4882a593Smuzhiyun extern int pci_is_66mhz_capable(struct pci_channel *hose,
61*4882a593Smuzhiyun int top_bus, int current_bus);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #define HAVE_PCI_MMAP
66*4882a593Smuzhiyun #define ARCH_GENERIC_PCI_MMAP_RESOURCE
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* Dynamic DMA mapping stuff.
69*4882a593Smuzhiyun * SuperH has everything mapped statically like x86.
70*4882a593Smuzhiyun */
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #ifdef CONFIG_PCI
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun * None of the SH PCI controllers support MWI, it is always treated as a
75*4882a593Smuzhiyun * direct memory write.
76*4882a593Smuzhiyun */
77*4882a593Smuzhiyun #define PCI_DISABLE_MWI
78*4882a593Smuzhiyun #endif
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* Board-specific fixup routines. */
81*4882a593Smuzhiyun int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
84*4882a593Smuzhiyun
pci_proc_domain(struct pci_bus * bus)85*4882a593Smuzhiyun static inline int pci_proc_domain(struct pci_bus *bus)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun struct pci_channel *hose = bus->sysdata;
88*4882a593Smuzhiyun return hose->need_domain_info;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* Chances are this interrupt is wired PC-style ... */
pci_get_legacy_ide_irq(struct pci_dev * dev,int channel)92*4882a593Smuzhiyun static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun return channel ? 15 : 14;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #endif /* __ASM_SH_PCI_H */
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