1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_MMU_CONTEXT_32_H 3*4882a593Smuzhiyun #define __ASM_SH_MMU_CONTEXT_32_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * Destroy context related info for an mm_struct that is about 7*4882a593Smuzhiyun * to be put to rest. 8*4882a593Smuzhiyun */ destroy_context(struct mm_struct * mm)9*4882a593Smuzhiyunstatic inline void destroy_context(struct mm_struct *mm) 10*4882a593Smuzhiyun { 11*4882a593Smuzhiyun /* Do nothing */ 12*4882a593Smuzhiyun } 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifdef CONFIG_CPU_HAS_PTEAEX set_asid(unsigned long asid)15*4882a593Smuzhiyunstatic inline void set_asid(unsigned long asid) 16*4882a593Smuzhiyun { 17*4882a593Smuzhiyun __raw_writel(asid, MMU_PTEAEX); 18*4882a593Smuzhiyun } 19*4882a593Smuzhiyun get_asid(void)20*4882a593Smuzhiyunstatic inline unsigned long get_asid(void) 21*4882a593Smuzhiyun { 22*4882a593Smuzhiyun return __raw_readl(MMU_PTEAEX) & MMU_CONTEXT_ASID_MASK; 23*4882a593Smuzhiyun } 24*4882a593Smuzhiyun #else set_asid(unsigned long asid)25*4882a593Smuzhiyunstatic inline void set_asid(unsigned long asid) 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun unsigned long __dummy; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun __asm__ __volatile__ ("mov.l %2, %0\n\t" 30*4882a593Smuzhiyun "and %3, %0\n\t" 31*4882a593Smuzhiyun "or %1, %0\n\t" 32*4882a593Smuzhiyun "mov.l %0, %2" 33*4882a593Smuzhiyun : "=&r" (__dummy) 34*4882a593Smuzhiyun : "r" (asid), "m" (__m(MMU_PTEH)), 35*4882a593Smuzhiyun "r" (0xffffff00)); 36*4882a593Smuzhiyun } 37*4882a593Smuzhiyun get_asid(void)38*4882a593Smuzhiyunstatic inline unsigned long get_asid(void) 39*4882a593Smuzhiyun { 40*4882a593Smuzhiyun unsigned long asid; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun __asm__ __volatile__ ("mov.l %1, %0" 43*4882a593Smuzhiyun : "=r" (asid) 44*4882a593Smuzhiyun : "m" (__m(MMU_PTEH))); 45*4882a593Smuzhiyun asid &= MMU_CONTEXT_ASID_MASK; 46*4882a593Smuzhiyun return asid; 47*4882a593Smuzhiyun } 48*4882a593Smuzhiyun #endif /* CONFIG_CPU_HAS_PTEAEX */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* MMU_TTB is used for optimizing the fault handling. */ set_TTB(pgd_t * pgd)51*4882a593Smuzhiyunstatic inline void set_TTB(pgd_t *pgd) 52*4882a593Smuzhiyun { 53*4882a593Smuzhiyun __raw_writel((unsigned long)pgd, MMU_TTB); 54*4882a593Smuzhiyun } 55*4882a593Smuzhiyun get_TTB(void)56*4882a593Smuzhiyunstatic inline pgd_t *get_TTB(void) 57*4882a593Smuzhiyun { 58*4882a593Smuzhiyun return (pgd_t *)__raw_readl(MMU_TTB); 59*4882a593Smuzhiyun } 60*4882a593Smuzhiyun #endif /* __ASM_SH_MMU_CONTEXT_32_H */ 61