1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_HW_IRQ_H 3*4882a593Smuzhiyun #define __ASM_SH_HW_IRQ_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/init.h> 6*4882a593Smuzhiyun #include <linux/sh_intc.h> 7*4882a593Smuzhiyun #include <linux/atomic.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun extern atomic_t irq_err_count; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct ipr_data { 12*4882a593Smuzhiyun unsigned char irq; 13*4882a593Smuzhiyun unsigned char ipr_idx; /* Index for the IPR registered */ 14*4882a593Smuzhiyun unsigned char shift; /* Number of bits to shift the data */ 15*4882a593Smuzhiyun unsigned char priority; /* The priority */ 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun struct ipr_desc { 19*4882a593Smuzhiyun unsigned long *ipr_offsets; 20*4882a593Smuzhiyun unsigned int nr_offsets; 21*4882a593Smuzhiyun struct ipr_data *ipr_data; 22*4882a593Smuzhiyun unsigned int nr_irqs; 23*4882a593Smuzhiyun struct irq_chip chip; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun void register_ipr_controller(struct ipr_desc *); 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun void __init plat_irq_setup(void); 29*4882a593Smuzhiyun void __init plat_irq_setup_sh3(void); 30*4882a593Smuzhiyun void __init plat_irq_setup_pins(int mode); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210, 33*4882a593Smuzhiyun IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK, 34*4882a593Smuzhiyun IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* __ASM_SH_HW_IRQ_H */ 37