1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_HD64461 3*4882a593Smuzhiyun #define __ASM_SH_HD64461 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> 6*4882a593Smuzhiyun * Copyright (C) 2004 Paul Mundt 7*4882a593Smuzhiyun * Copyright (C) 2000 YAEGASHI Takeshi 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Hitachi HD64461 companion chip support 10*4882a593Smuzhiyun * (please note manual reference 0x10000000 = 0xb0000000) 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Constants for PCMCIA mappings */ 14*4882a593Smuzhiyun #define HD64461_PCC_WINDOW 0x01000000 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Area 6 - Slot 0 - memory and/or IO card */ 17*4882a593Smuzhiyun #define HD64461_IOBASE 0xb0000000 18*4882a593Smuzhiyun #define HD64461_IO_OFFSET(x) (HD64461_IOBASE + (x)) 19*4882a593Smuzhiyun #define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000) 20*4882a593Smuzhiyun #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */ 21*4882a593Smuzhiyun #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */ 22*4882a593Smuzhiyun #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Area 5 - Slot 1 - memory card only */ 25*4882a593Smuzhiyun #define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000) 26*4882a593Smuzhiyun #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */ 27*4882a593Smuzhiyun #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Standby Control Register for HD64461 */ 30*4882a593Smuzhiyun #define HD64461_STBCR HD64461_IO_OFFSET(0x00000000) 31*4882a593Smuzhiyun #define HD64461_STBCR_CKIO_STBY 0x2000 32*4882a593Smuzhiyun #define HD64461_STBCR_SAFECKE_IST 0x1000 33*4882a593Smuzhiyun #define HD64461_STBCR_SLCKE_IST 0x0800 34*4882a593Smuzhiyun #define HD64461_STBCR_SAFECKE_OST 0x0400 35*4882a593Smuzhiyun #define HD64461_STBCR_SLCKE_OST 0x0200 36*4882a593Smuzhiyun #define HD64461_STBCR_SMIAST 0x0100 37*4882a593Smuzhiyun #define HD64461_STBCR_SLCDST 0x0080 38*4882a593Smuzhiyun #define HD64461_STBCR_SPC0ST 0x0040 39*4882a593Smuzhiyun #define HD64461_STBCR_SPC1ST 0x0020 40*4882a593Smuzhiyun #define HD64461_STBCR_SAFEST 0x0010 41*4882a593Smuzhiyun #define HD64461_STBCR_STM0ST 0x0008 42*4882a593Smuzhiyun #define HD64461_STBCR_STM1ST 0x0004 43*4882a593Smuzhiyun #define HD64461_STBCR_SIRST 0x0002 44*4882a593Smuzhiyun #define HD64461_STBCR_SURTST 0x0001 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* System Configuration Register */ 47*4882a593Smuzhiyun #define HD64461_SYSCR HD64461_IO_OFFSET(0x02) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* CPU Data Bus Control Register */ 50*4882a593Smuzhiyun #define HD64461_SCPUCR HD64461_IO_OFFSET(0x04) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Base Address Register */ 53*4882a593Smuzhiyun #define HD64461_LCDCBAR HD64461_IO_OFFSET(0x1000) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Line increment address */ 56*4882a593Smuzhiyun #define HD64461_LCDCLOR HD64461_IO_OFFSET(0x1002) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Controls LCD controller */ 59*4882a593Smuzhiyun #define HD64461_LCDCCR HD64461_IO_OFFSET(0x1004) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* LCCDR control bits */ 62*4882a593Smuzhiyun #define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */ 63*4882a593Smuzhiyun #define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */ 64*4882a593Smuzhiyun #define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */ 65*4882a593Smuzhiyun #define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */ 66*4882a593Smuzhiyun #define HD64461_LCDCCR_EPON 0x0020 /* End Power On */ 67*4882a593Smuzhiyun #define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* Controls LCD (1) */ 70*4882a593Smuzhiyun #define HD64461_LDR1 HD64461_IO_OFFSET(0x1010) 71*4882a593Smuzhiyun #define HD64461_LDR1_DON 0x01 /* Display On */ 72*4882a593Smuzhiyun #define HD64461_LDR1_DINV 0x80 /* Display Invert */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* Controls LCD (2) */ 75*4882a593Smuzhiyun #define HD64461_LDR2 HD64461_IO_OFFSET(0x1012) 76*4882a593Smuzhiyun #define HD64461_LDHNCR HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */ 77*4882a593Smuzhiyun #define HD64461_LDHNSR HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */ 78*4882a593Smuzhiyun #define HD64461_LDVNTR HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */ 79*4882a593Smuzhiyun #define HD64461_LDVNDR HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */ 80*4882a593Smuzhiyun #define HD64461_LDVSPR HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Controls LCD (3) */ 83*4882a593Smuzhiyun #define HD64461_LDR3 HD64461_IO_OFFSET(0x101e) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Palette Registers */ 86*4882a593Smuzhiyun #define HD64461_CPTWAR HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */ 87*4882a593Smuzhiyun #define HD64461_CPTWDR HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */ 88*4882a593Smuzhiyun #define HD64461_CPTRAR HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */ 89*4882a593Smuzhiyun #define HD64461_CPTRDR HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define HD64461_GRDOR HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */ 92*4882a593Smuzhiyun #define HD64461_GRSCR HD64461_IO_OFFSET(0x1042) /* Solid Color Register */ 93*4882a593Smuzhiyun #define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */ 96*4882a593Smuzhiyun #define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */ 97*4882a593Smuzhiyun #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */ 98*4882a593Smuzhiyun #define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */ 99*4882a593Smuzhiyun #define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */ 100*4882a593Smuzhiyun #define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* Line Drawing Registers */ 103*4882a593Smuzhiyun #define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */ 104*4882a593Smuzhiyun #define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */ 105*4882a593Smuzhiyun #define HD64461_LNAXLR HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */ 106*4882a593Smuzhiyun #define HD64461_LNDGR HD64461_IO_OFFSET(0x104c) /* Diagonal Register */ 107*4882a593Smuzhiyun #define HD64461_LNAXR HD64461_IO_OFFSET(0x104e) /* Axial Register */ 108*4882a593Smuzhiyun #define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */ 109*4882a593Smuzhiyun #define HD64461_LNMDR HD64461_IO_OFFSET(0x1052) /* Line Mode Register */ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* BitBLT Registers */ 112*4882a593Smuzhiyun #define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */ 113*4882a593Smuzhiyun #define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */ 114*4882a593Smuzhiyun #define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */ 115*4882a593Smuzhiyun #define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */ 116*4882a593Smuzhiyun #define HD64461_BBTDWR HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */ 117*4882a593Smuzhiyun #define HD64461_BBTDHR HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */ 118*4882a593Smuzhiyun #define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */ 119*4882a593Smuzhiyun #define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */ 120*4882a593Smuzhiyun #define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */ 121*4882a593Smuzhiyun #define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */ 122*4882a593Smuzhiyun #define HD64461_BBTROPR HD64461_IO_OFFSET(0x1068) /* ROP Register */ 123*4882a593Smuzhiyun #define HD64461_BBTMDR HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */ 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* PC Card Controller Registers */ 126*4882a593Smuzhiyun /* Maps to Physical Area 6 */ 127*4882a593Smuzhiyun #define HD64461_PCC0ISR HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */ 128*4882a593Smuzhiyun #define HD64461_PCC0GCR HD64461_IO_OFFSET(0x2002) /* socket 0 general control */ 129*4882a593Smuzhiyun #define HD64461_PCC0CSCR HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */ 130*4882a593Smuzhiyun #define HD64461_PCC0CSCIER HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */ 131*4882a593Smuzhiyun #define HD64461_PCC0SCR HD64461_IO_OFFSET(0x2008) /* socket 0 software control */ 132*4882a593Smuzhiyun /* Maps to Physical Area 5 */ 133*4882a593Smuzhiyun #define HD64461_PCC1ISR HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */ 134*4882a593Smuzhiyun #define HD64461_PCC1GCR HD64461_IO_OFFSET(0x2012) /* socket 1 general control */ 135*4882a593Smuzhiyun #define HD64461_PCC1CSCR HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */ 136*4882a593Smuzhiyun #define HD64461_PCC1CSCIER HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */ 137*4882a593Smuzhiyun #define HD64461_PCC1SCR HD64461_IO_OFFSET(0x2018) /* socket 1 software control */ 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* PCC Interface Status Register */ 140*4882a593Smuzhiyun #define HD64461_PCCISR_READY 0x80 /* card ready */ 141*4882a593Smuzhiyun #define HD64461_PCCISR_MWP 0x40 /* card write-protected */ 142*4882a593Smuzhiyun #define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ 143*4882a593Smuzhiyun #define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ 144*4882a593Smuzhiyun #define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ 145*4882a593Smuzhiyun #define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ 146*4882a593Smuzhiyun #define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ 147*4882a593Smuzhiyun #define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ 150*4882a593Smuzhiyun #define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ 151*4882a593Smuzhiyun #define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ 152*4882a593Smuzhiyun #define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ 153*4882a593Smuzhiyun #define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ 154*4882a593Smuzhiyun #define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* PCC General Control Register */ 157*4882a593Smuzhiyun #define HD64461_PCCGCR_DRVE 0x80 /* output drive */ 158*4882a593Smuzhiyun #define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ 159*4882a593Smuzhiyun #define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ 160*4882a593Smuzhiyun #define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ 161*4882a593Smuzhiyun #define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ 162*4882a593Smuzhiyun #define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ 163*4882a593Smuzhiyun #define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ 164*4882a593Smuzhiyun #define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* PCC Card Status Change Register */ 167*4882a593Smuzhiyun #define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ 168*4882a593Smuzhiyun #define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ 169*4882a593Smuzhiyun #define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ 170*4882a593Smuzhiyun #define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ 171*4882a593Smuzhiyun #define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ 172*4882a593Smuzhiyun #define HD64461_PCCCSCR_RC 0x04 /* READY change */ 173*4882a593Smuzhiyun #define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ 174*4882a593Smuzhiyun #define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* PCC Card Status Change Interrupt Enable Register */ 177*4882a593Smuzhiyun #define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ 178*4882a593Smuzhiyun #define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ 179*4882a593Smuzhiyun #define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ 180*4882a593Smuzhiyun #define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ 181*4882a593Smuzhiyun #define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ 182*4882a593Smuzhiyun #define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ 185*4882a593Smuzhiyun #define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ 186*4882a593Smuzhiyun #define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ 187*4882a593Smuzhiyun #define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ 188*4882a593Smuzhiyun #define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun /* PCC Software Control Register */ 191*4882a593Smuzhiyun #define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ 192*4882a593Smuzhiyun #define HD64461_PCCSCR_SWP 0x01 /* write protect */ 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* PCC0 Output Pins Control Register */ 195*4882a593Smuzhiyun #define HD64461_P0OCR HD64461_IO_OFFSET(0x202a) 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun /* PCC1 Output Pins Control Register */ 198*4882a593Smuzhiyun #define HD64461_P1OCR HD64461_IO_OFFSET(0x202c) 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun /* PC Card General Control Register */ 201*4882a593Smuzhiyun #define HD64461_PGCR HD64461_IO_OFFSET(0x202e) 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* Port Control Registers */ 204*4882a593Smuzhiyun #define HD64461_GPACR HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */ 205*4882a593Smuzhiyun #define HD64461_GPBCR HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */ 206*4882a593Smuzhiyun #define HD64461_GPCCR HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */ 207*4882a593Smuzhiyun #define HD64461_GPDCR HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */ 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun /* Port Control Data Registers */ 210*4882a593Smuzhiyun #define HD64461_GPADR HD64461_IO_OFFSET(0x4010) /* A */ 211*4882a593Smuzhiyun #define HD64461_GPBDR HD64461_IO_OFFSET(0x4012) /* B */ 212*4882a593Smuzhiyun #define HD64461_GPCDR HD64461_IO_OFFSET(0x4014) /* C */ 213*4882a593Smuzhiyun #define HD64461_GPDDR HD64461_IO_OFFSET(0x4016) /* D */ 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun /* Interrupt Control Registers */ 216*4882a593Smuzhiyun #define HD64461_GPAICR HD64461_IO_OFFSET(0x4020) /* A */ 217*4882a593Smuzhiyun #define HD64461_GPBICR HD64461_IO_OFFSET(0x4022) /* B */ 218*4882a593Smuzhiyun #define HD64461_GPCICR HD64461_IO_OFFSET(0x4024) /* C */ 219*4882a593Smuzhiyun #define HD64461_GPDICR HD64461_IO_OFFSET(0x4026) /* D */ 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun /* Interrupt Status Registers */ 222*4882a593Smuzhiyun #define HD64461_GPAISR HD64461_IO_OFFSET(0x4040) /* A */ 223*4882a593Smuzhiyun #define HD64461_GPBISR HD64461_IO_OFFSET(0x4042) /* B */ 224*4882a593Smuzhiyun #define HD64461_GPCISR HD64461_IO_OFFSET(0x4044) /* C */ 225*4882a593Smuzhiyun #define HD64461_GPDISR HD64461_IO_OFFSET(0x4046) /* D */ 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun /* Interrupt Request Register & Interrupt Mask Register */ 228*4882a593Smuzhiyun #define HD64461_NIRR HD64461_IO_OFFSET(0x5000) 229*4882a593Smuzhiyun #define HD64461_NIMR HD64461_IO_OFFSET(0x5002) 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #define HD64461_IRQBASE OFFCHIP_IRQ_BASE 232*4882a593Smuzhiyun #define OFFCHIP_IRQ_BASE 64 233*4882a593Smuzhiyun #define HD64461_IRQ_NUM 16 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun #define HD64461_IRQ_UART (HD64461_IRQBASE+5) 236*4882a593Smuzhiyun #define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) 237*4882a593Smuzhiyun #define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) 238*4882a593Smuzhiyun #define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) 239*4882a593Smuzhiyun #define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) 240*4882a593Smuzhiyun #define HD64461_IRQ_AFE (HD64461_IRQBASE+12) 241*4882a593Smuzhiyun #define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) 242*4882a593Smuzhiyun #define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun #define __IO_PREFIX hd64461 245*4882a593Smuzhiyun #include <asm/io_generic.h> 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun /* arch/sh/cchips/hd6446x/hd64461/setup.c */ 248*4882a593Smuzhiyun void hd64461_register_irq_demux(int irq, 249*4882a593Smuzhiyun int (*demux) (int irq, void *dev), void *dev); 250*4882a593Smuzhiyun void hd64461_unregister_irq_demux(int irq); 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun #endif 253