1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * include/asm-sh/dma.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2003, 2004 Paul Mundt 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __ASM_SH_DMA_H 8*4882a593Smuzhiyun #define __ASM_SH_DMA_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/spinlock.h> 11*4882a593Smuzhiyun #include <linux/wait.h> 12*4882a593Smuzhiyun #include <linux/sched.h> 13*4882a593Smuzhiyun #include <linux/device.h> 14*4882a593Smuzhiyun #include <asm-generic/dma.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * Read and write modes can mean drastically different things depending on the 18*4882a593Smuzhiyun * channel configuration. Consult your DMAC documentation and module 19*4882a593Smuzhiyun * implementation for further clues. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #define DMA_MODE_READ 0x00 22*4882a593Smuzhiyun #define DMA_MODE_WRITE 0x01 23*4882a593Smuzhiyun #define DMA_MODE_MASK 0x01 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define DMA_AUTOINIT 0x10 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * DMAC (dma_info) flags 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun enum { 31*4882a593Smuzhiyun DMAC_CHANNELS_CONFIGURED = 0x01, 32*4882a593Smuzhiyun DMAC_CHANNELS_TEI_CAPABLE = 0x02, /* Transfer end interrupt */ 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * DMA channel capabilities / flags 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun enum { 39*4882a593Smuzhiyun DMA_CONFIGURED = 0x01, 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * Transfer end interrupt, inherited from DMAC. 43*4882a593Smuzhiyun * wait_queue used in dma_wait_for_completion. 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun DMA_TEI_CAPABLE = 0x02, 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun extern spinlock_t dma_spin_lock; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun struct dma_channel; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct dma_ops { 53*4882a593Smuzhiyun int (*request)(struct dma_channel *chan); 54*4882a593Smuzhiyun void (*free)(struct dma_channel *chan); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun int (*get_residue)(struct dma_channel *chan); 57*4882a593Smuzhiyun int (*xfer)(struct dma_channel *chan); 58*4882a593Smuzhiyun int (*configure)(struct dma_channel *chan, unsigned long flags); 59*4882a593Smuzhiyun int (*extend)(struct dma_channel *chan, unsigned long op, void *param); 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct dma_channel { 63*4882a593Smuzhiyun char dev_id[16]; /* unique name per DMAC of channel */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun unsigned int chan; /* DMAC channel number */ 66*4882a593Smuzhiyun unsigned int vchan; /* Virtual channel number */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun unsigned int mode; 69*4882a593Smuzhiyun unsigned int count; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun unsigned long sar; 72*4882a593Smuzhiyun unsigned long dar; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun const char **caps; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun unsigned long flags; 77*4882a593Smuzhiyun atomic_t busy; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun wait_queue_head_t wait_queue; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun struct device dev; 82*4882a593Smuzhiyun void *priv_data; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun struct dma_info { 86*4882a593Smuzhiyun struct platform_device *pdev; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun const char *name; 89*4882a593Smuzhiyun unsigned int nr_channels; 90*4882a593Smuzhiyun unsigned long flags; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun struct dma_ops *ops; 93*4882a593Smuzhiyun struct dma_channel *channels; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun struct list_head list; 96*4882a593Smuzhiyun int first_channel_nr; 97*4882a593Smuzhiyun int first_vchannel_nr; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun struct dma_chan_caps { 101*4882a593Smuzhiyun int ch_num; 102*4882a593Smuzhiyun const char **caplist; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define to_dma_channel(channel) container_of(channel, struct dma_channel, dev) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* arch/sh/drivers/dma/dma-api.c */ 108*4882a593Smuzhiyun extern int dma_xfer(unsigned int chan, unsigned long from, 109*4882a593Smuzhiyun unsigned long to, size_t size, unsigned int mode); 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define dma_write(chan, from, to, size) \ 112*4882a593Smuzhiyun dma_xfer(chan, from, to, size, DMA_MODE_WRITE) 113*4882a593Smuzhiyun #define dma_write_page(chan, from, to) \ 114*4882a593Smuzhiyun dma_write(chan, from, to, PAGE_SIZE) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define dma_read(chan, from, to, size) \ 117*4882a593Smuzhiyun dma_xfer(chan, from, to, size, DMA_MODE_READ) 118*4882a593Smuzhiyun #define dma_read_page(chan, from, to) \ 119*4882a593Smuzhiyun dma_read(chan, from, to, PAGE_SIZE) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun extern int request_dma_bycap(const char **dmac, const char **caps, 122*4882a593Smuzhiyun const char *dev_id); 123*4882a593Smuzhiyun extern int get_dma_residue(unsigned int chan); 124*4882a593Smuzhiyun extern struct dma_info *get_dma_info(unsigned int chan); 125*4882a593Smuzhiyun extern struct dma_channel *get_dma_channel(unsigned int chan); 126*4882a593Smuzhiyun extern void dma_wait_for_completion(unsigned int chan); 127*4882a593Smuzhiyun extern void dma_configure_channel(unsigned int chan, unsigned long flags); 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun extern int register_dmac(struct dma_info *info); 130*4882a593Smuzhiyun extern void unregister_dmac(struct dma_info *info); 131*4882a593Smuzhiyun extern struct dma_info *get_dma_info_by_name(const char *dmac_name); 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun extern int dma_extend(unsigned int chan, unsigned long op, void *param); 134*4882a593Smuzhiyun extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist); 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* arch/sh/drivers/dma/dma-sysfs.c */ 137*4882a593Smuzhiyun extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *); 138*4882a593Smuzhiyun extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *); 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #ifdef CONFIG_PCI 141*4882a593Smuzhiyun extern int isa_dma_bridge_buggy; 142*4882a593Smuzhiyun #else 143*4882a593Smuzhiyun #define isa_dma_bridge_buggy (0) 144*4882a593Smuzhiyun #endif 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #endif /* __ASM_SH_DMA_H */ 147