1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Common header for the legacy SH DMA driver and the new dmaengine driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * extracted from arch/sh/include/asm/dma-sh.h: 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2000 Takashi YOSHII 8*4882a593Smuzhiyun * Copyright (C) 2003 Paul Mundt 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef DMA_REGISTER_H 11*4882a593Smuzhiyun #define DMA_REGISTER_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* DMA registers */ 14*4882a593Smuzhiyun #define SAR 0x00 /* Source Address Register */ 15*4882a593Smuzhiyun #define DAR 0x04 /* Destination Address Register */ 16*4882a593Smuzhiyun #define TCR 0x08 /* Transfer Count Register */ 17*4882a593Smuzhiyun #define CHCR 0x0C /* Channel Control Register */ 18*4882a593Smuzhiyun #define DMAOR 0x40 /* DMA Operation Register */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* DMAOR definitions */ 21*4882a593Smuzhiyun #define DMAOR_AE 0x00000004 /* Address Error Flag */ 22*4882a593Smuzhiyun #define DMAOR_NMIF 0x00000002 23*4882a593Smuzhiyun #define DMAOR_DME 0x00000001 /* DMA Master Enable */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Definitions for the SuperH DMAC */ 26*4882a593Smuzhiyun #define REQ_L 0x00000000 27*4882a593Smuzhiyun #define REQ_E 0x00080000 28*4882a593Smuzhiyun #define RACK_H 0x00000000 29*4882a593Smuzhiyun #define RACK_L 0x00040000 30*4882a593Smuzhiyun #define ACK_R 0x00000000 31*4882a593Smuzhiyun #define ACK_W 0x00020000 32*4882a593Smuzhiyun #define ACK_H 0x00000000 33*4882a593Smuzhiyun #define ACK_L 0x00010000 34*4882a593Smuzhiyun #define DM_INC 0x00004000 /* Destination addresses are incremented */ 35*4882a593Smuzhiyun #define DM_DEC 0x00008000 /* Destination addresses are decremented */ 36*4882a593Smuzhiyun #define DM_FIX 0x0000c000 /* Destination address is fixed */ 37*4882a593Smuzhiyun #define SM_INC 0x00001000 /* Source addresses are incremented */ 38*4882a593Smuzhiyun #define SM_DEC 0x00002000 /* Source addresses are decremented */ 39*4882a593Smuzhiyun #define SM_FIX 0x00003000 /* Source address is fixed */ 40*4882a593Smuzhiyun #define RS_IN 0x00000200 41*4882a593Smuzhiyun #define RS_OUT 0x00000300 42*4882a593Smuzhiyun #define RS_AUTO 0x00000400 /* Auto Request */ 43*4882a593Smuzhiyun #define RS_ERS 0x00000800 /* DMA extended resource selector */ 44*4882a593Smuzhiyun #define TS_BLK 0x00000040 45*4882a593Smuzhiyun #define TM_BUR 0x00000020 46*4882a593Smuzhiyun #define CHCR_DE 0x00000001 /* DMA Enable */ 47*4882a593Smuzhiyun #define CHCR_TE 0x00000002 /* Transfer End Flag */ 48*4882a593Smuzhiyun #define CHCR_IE 0x00000004 /* Interrupt Enable */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif 51