1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_CACHE_INSNS_32_H 3*4882a593Smuzhiyun #define __ASM_SH_CACHE_INSNS_32_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/types.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #if defined(CONFIG_CPU_SH4A) 8*4882a593Smuzhiyun #define __icbi(addr) __asm__ __volatile__ ( "icbi @%0\n\t" : : "r" (addr)) 9*4882a593Smuzhiyun #else 10*4882a593Smuzhiyun #define __icbi(addr) mb() 11*4882a593Smuzhiyun #endif 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define __ocbp(addr) __asm__ __volatile__ ( "ocbp @%0\n\t" : : "r" (addr)) 14*4882a593Smuzhiyun #define __ocbi(addr) __asm__ __volatile__ ( "ocbi @%0\n\t" : : "r" (addr)) 15*4882a593Smuzhiyun #define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb @%0\n\t" : : "r" (addr)) 16*4882a593Smuzhiyun register_align(void * val)17*4882a593Smuzhiyunstatic inline reg_size_t register_align(void *val) 18*4882a593Smuzhiyun { 19*4882a593Smuzhiyun return (unsigned long)(signed long)val; 20*4882a593Smuzhiyun } 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #endif /* __ASM_SH_CACHE_INSNS_32_H */ 23