1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima 4*4882a593Smuzhiyun * Copyright (C) 2002 Paul Mundt 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __ASM_SH_BARRIER_H 7*4882a593Smuzhiyun #define __ASM_SH_BARRIER_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #if defined(CONFIG_CPU_SH4A) 10*4882a593Smuzhiyun #include <asm/cache_insns.h> 11*4882a593Smuzhiyun #endif 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * A brief note on ctrl_barrier(), the control register write barrier. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * Legacy SH cores typically require a sequence of 8 nops after 17*4882a593Smuzhiyun * modification of a control register in order for the changes to take 18*4882a593Smuzhiyun * effect. On newer cores (like the sh4a and sh5) this is accomplished 19*4882a593Smuzhiyun * with icbi. 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * Also note that on sh4a in the icbi case we can forego a synco for the 22*4882a593Smuzhiyun * write barrier, as it's not necessary for control registers. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * Historically we have only done this type of barrier for the MMUCR, but 25*4882a593Smuzhiyun * it's also necessary for the CCR, so we make it generic here instead. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #if defined(CONFIG_CPU_SH4A) 28*4882a593Smuzhiyun #define mb() __asm__ __volatile__ ("synco": : :"memory") 29*4882a593Smuzhiyun #define rmb() mb() 30*4882a593Smuzhiyun #define wmb() mb() 31*4882a593Smuzhiyun #define ctrl_barrier() __icbi(PAGE_OFFSET) 32*4882a593Smuzhiyun #else 33*4882a593Smuzhiyun #if defined(CONFIG_CPU_J2) && defined(CONFIG_SMP) 34*4882a593Smuzhiyun #define __smp_mb() do { int tmp = 0; __asm__ __volatile__ ("cas.l %0,%0,@%1" : "+r"(tmp) : "z"(&tmp) : "memory", "t"); } while(0) 35*4882a593Smuzhiyun #define __smp_rmb() __smp_mb() 36*4882a593Smuzhiyun #define __smp_wmb() __smp_mb() 37*4882a593Smuzhiyun #endif 38*4882a593Smuzhiyun #define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") 39*4882a593Smuzhiyun #endif 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #include <asm-generic/barrier.h> 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif /* __ASM_SH_BARRIER_H */ 46