1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 1999 by Kaz Kojima 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Defitions for the address spaces of the SH CPUs. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __ASM_SH_ADDRSPACE_H 8*4882a593Smuzhiyun #define __ASM_SH_ADDRSPACE_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <cpu/addrspace.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* If this CPU supports segmentation, hook up the helpers */ 13*4882a593Smuzhiyun #ifdef P1SEG 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun [ P0/U0 (virtual) ] 0x00000000 <------ User space 17*4882a593Smuzhiyun [ P1 (fixed) cached ] 0x80000000 <------ Kernel space 18*4882a593Smuzhiyun [ P2 (fixed) non-cachable] 0xA0000000 <------ Physical access 19*4882a593Smuzhiyun [ P3 (virtual) cached] 0xC0000000 <------ vmalloced area 20*4882a593Smuzhiyun [ P4 control ] 0xE0000000 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* Returns the privileged segment base of a given address */ 24*4882a593Smuzhiyun #define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #ifdef CONFIG_29BIT 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * Map an address to a certain privileged segment 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #define P1SEGADDR(a) \ 31*4882a593Smuzhiyun ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) 32*4882a593Smuzhiyun #define P2SEGADDR(a) \ 33*4882a593Smuzhiyun ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) 34*4882a593Smuzhiyun #define P3SEGADDR(a) \ 35*4882a593Smuzhiyun ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) 36*4882a593Smuzhiyun #define P4SEGADDR(a) \ 37*4882a593Smuzhiyun ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) 38*4882a593Smuzhiyun #else 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * These will never work in 32-bit, don't even bother. 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun #define P1SEGADDR(a) ({ (void)(a); BUG(); NULL; }) 43*4882a593Smuzhiyun #define P2SEGADDR(a) ({ (void)(a); BUG(); NULL; }) 44*4882a593Smuzhiyun #define P3SEGADDR(a) ({ (void)(a); BUG(); NULL; }) 45*4882a593Smuzhiyun #define P4SEGADDR(a) ({ (void)(a); BUG(); NULL; }) 46*4882a593Smuzhiyun #endif 47*4882a593Smuzhiyun #endif /* P1SEG */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Check if an address can be reached in 29 bits */ 50*4882a593Smuzhiyun #define IS_29BIT(a) (((unsigned long)(a)) < 0x20000000) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #ifdef CONFIG_SH_STORE_QUEUES 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * This is a special case for the SH-4 store queues, as pages for this 55*4882a593Smuzhiyun * space still need to be faulted in before it's possible to flush the 56*4882a593Smuzhiyun * store queue cache for writeout to the remapped region. 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define P3_ADDR_MAX (P4SEG_STORE_QUE + 0x04000000) 59*4882a593Smuzhiyun #else 60*4882a593Smuzhiyun #define P3_ADDR_MAX P4SEG 61*4882a593Smuzhiyun #endif 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif /* __ASM_SH_ADDRSPACE_H */ 64