xref: /OK3568_Linux_fs/kernel/arch/sh/drivers/superhyway/ops-sh4-202.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * arch/sh/drivers/superhyway/ops-sh4-202.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SuperHyway bus support for SH4-202
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (C) 2005  Paul Mundt
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/superhyway.h>
12*4882a593Smuzhiyun #include <linux/string.h>
13*4882a593Smuzhiyun #include <asm/addrspace.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define PHYS_EMI_CBLOCK		P4SEGADDR(0x1ec00000)
17*4882a593Smuzhiyun #define PHYS_EMI_DBLOCK		P4SEGADDR(0x08000000)
18*4882a593Smuzhiyun #define PHYS_FEMI_CBLOCK	P4SEGADDR(0x1f800000)
19*4882a593Smuzhiyun #define PHYS_FEMI_DBLOCK	P4SEGADDR(0x00000000)
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define PHYS_EPBR_BLOCK		P4SEGADDR(0x1de00000)
22*4882a593Smuzhiyun #define PHYS_DMAC_BLOCK		P4SEGADDR(0x1fa00000)
23*4882a593Smuzhiyun #define PHYS_PBR_BLOCK		P4SEGADDR(0x1fc00000)
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun static struct resource emi_resources[] = {
26*4882a593Smuzhiyun 	[0] = {
27*4882a593Smuzhiyun 		.start	= PHYS_EMI_CBLOCK,
28*4882a593Smuzhiyun 		.end	= PHYS_EMI_CBLOCK + 0x00300000 - 1,
29*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
30*4882a593Smuzhiyun 	},
31*4882a593Smuzhiyun 	[1] = {
32*4882a593Smuzhiyun 		.start	= PHYS_EMI_DBLOCK,
33*4882a593Smuzhiyun 		.end	= PHYS_EMI_DBLOCK + 0x08000000 - 1,
34*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
35*4882a593Smuzhiyun 	},
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun static struct superhyway_device emi_device = {
39*4882a593Smuzhiyun 	.name		= "emi",
40*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(emi_resources),
41*4882a593Smuzhiyun 	.resource	= emi_resources,
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun static struct resource femi_resources[] = {
45*4882a593Smuzhiyun 	[0] = {
46*4882a593Smuzhiyun 		.start	= PHYS_FEMI_CBLOCK,
47*4882a593Smuzhiyun 		.end	= PHYS_FEMI_CBLOCK + 0x00100000 - 1,
48*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
49*4882a593Smuzhiyun 	},
50*4882a593Smuzhiyun 	[1] = {
51*4882a593Smuzhiyun 		.start	= PHYS_FEMI_DBLOCK,
52*4882a593Smuzhiyun 		.end	= PHYS_FEMI_DBLOCK + 0x08000000 - 1,
53*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
54*4882a593Smuzhiyun 	},
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun static struct superhyway_device femi_device = {
58*4882a593Smuzhiyun 	.name		= "femi",
59*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(femi_resources),
60*4882a593Smuzhiyun 	.resource	= femi_resources,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun static struct resource epbr_resources[] = {
64*4882a593Smuzhiyun 	[0] = {
65*4882a593Smuzhiyun 		.start	= P4SEGADDR(0x1e7ffff8),
66*4882a593Smuzhiyun 		.end	= P4SEGADDR(0x1e7ffff8 + (sizeof(u32) * 2) - 1),
67*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
68*4882a593Smuzhiyun 	},
69*4882a593Smuzhiyun 	[1] = {
70*4882a593Smuzhiyun 		.start	= PHYS_EPBR_BLOCK,
71*4882a593Smuzhiyun 		.end	= PHYS_EPBR_BLOCK + 0x00a00000 - 1,
72*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
73*4882a593Smuzhiyun 	},
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun static struct superhyway_device epbr_device = {
77*4882a593Smuzhiyun 	.name		= "epbr",
78*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(epbr_resources),
79*4882a593Smuzhiyun 	.resource	= epbr_resources,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun static struct resource dmac_resource = {
83*4882a593Smuzhiyun 	.start	= PHYS_DMAC_BLOCK,
84*4882a593Smuzhiyun 	.end	= PHYS_DMAC_BLOCK + 0x00100000 - 1,
85*4882a593Smuzhiyun 	.flags	= IORESOURCE_MEM,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun static struct superhyway_device dmac_device = {
89*4882a593Smuzhiyun 	.name		= "dmac",
90*4882a593Smuzhiyun 	.num_resources	= 1,
91*4882a593Smuzhiyun 	.resource	= &dmac_resource,
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun static struct resource pbr_resources[] = {
95*4882a593Smuzhiyun 	[0] = {
96*4882a593Smuzhiyun 		.start	= P4SEGADDR(0x1ffffff8),
97*4882a593Smuzhiyun 		.end	= P4SEGADDR(0x1ffffff8 + (sizeof(u32) * 2) - 1),
98*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
99*4882a593Smuzhiyun 	},
100*4882a593Smuzhiyun 	[1] = {
101*4882a593Smuzhiyun 		.start	= PHYS_PBR_BLOCK,
102*4882a593Smuzhiyun 		.end	= PHYS_PBR_BLOCK + 0x00400000 - (sizeof(u32) * 2) - 1,
103*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
104*4882a593Smuzhiyun 	},
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun static struct superhyway_device pbr_device = {
108*4882a593Smuzhiyun 	.name		= "pbr",
109*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(pbr_resources),
110*4882a593Smuzhiyun 	.resource	= pbr_resources,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun static struct superhyway_device *sh4202_devices[] __initdata = {
114*4882a593Smuzhiyun 	&emi_device, &femi_device, &epbr_device, &dmac_device, &pbr_device,
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
sh4202_read_vcr(unsigned long base,struct superhyway_vcr_info * vcr)117*4882a593Smuzhiyun static int sh4202_read_vcr(unsigned long base, struct superhyway_vcr_info *vcr)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	u32 vcrh, vcrl;
120*4882a593Smuzhiyun 	u64 tmp;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	/*
123*4882a593Smuzhiyun 	 * XXX: Even though the SH4-202 Evaluation Device documentation
124*4882a593Smuzhiyun 	 * indicates that VCRL is mapped first with VCRH at a + 0x04
125*4882a593Smuzhiyun 	 * offset, the opposite seems to be true.
126*4882a593Smuzhiyun 	 *
127*4882a593Smuzhiyun 	 * Some modules (PBR and ePBR for instance) also appear to have
128*4882a593Smuzhiyun 	 * VCRL/VCRH flipped in the documentation, but on the SH4-202
129*4882a593Smuzhiyun 	 * itself it appears that these are all consistently mapped with
130*4882a593Smuzhiyun 	 * VCRH preceding VCRL.
131*4882a593Smuzhiyun 	 *
132*4882a593Smuzhiyun 	 * Do not trust the documentation, for it is evil.
133*4882a593Smuzhiyun 	 */
134*4882a593Smuzhiyun 	vcrh = __raw_readl(base);
135*4882a593Smuzhiyun 	vcrl = __raw_readl(base + sizeof(u32));
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	tmp = ((u64)vcrh << 32) | vcrl;
138*4882a593Smuzhiyun 	memcpy(vcr, &tmp, sizeof(u64));
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
sh4202_write_vcr(unsigned long base,struct superhyway_vcr_info vcr)143*4882a593Smuzhiyun static int sh4202_write_vcr(unsigned long base, struct superhyway_vcr_info vcr)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	u64 tmp = *(u64 *)&vcr;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	__raw_writel((tmp >> 32) & 0xffffffff, base);
148*4882a593Smuzhiyun 	__raw_writel(tmp & 0xffffffff, base + sizeof(u32));
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	return 0;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun static struct superhyway_ops sh4202_superhyway_ops = {
154*4882a593Smuzhiyun 	.read_vcr	= sh4202_read_vcr,
155*4882a593Smuzhiyun 	.write_vcr	= sh4202_write_vcr,
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun struct superhyway_bus superhyway_channels[] = {
159*4882a593Smuzhiyun 	{ &sh4202_superhyway_ops, },
160*4882a593Smuzhiyun 	{ 0, },
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
superhyway_scan_bus(struct superhyway_bus * bus)163*4882a593Smuzhiyun int __init superhyway_scan_bus(struct superhyway_bus *bus)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun 	return superhyway_add_devices(bus, sh4202_devices,
166*4882a593Smuzhiyun 				      ARRAY_SIZE(sh4202_devices));
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun 
169