1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2002 - 2009 Paul Mundt
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/pci.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/spinlock.h>
10*4882a593Smuzhiyun #include <asm/addrspace.h>
11*4882a593Smuzhiyun #include "pci-sh4.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun * Direct access to PCI hardware...
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun #define CONFIG_CMD(bus, devfn, where) \
17*4882a593Smuzhiyun (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * Functions for accessing PCI configuration space with type 1 accesses
21*4882a593Smuzhiyun */
sh4_pci_read(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)22*4882a593Smuzhiyun static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
23*4882a593Smuzhiyun int where, int size, u32 *val)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun struct pci_channel *chan = bus->sysdata;
26*4882a593Smuzhiyun unsigned long flags;
27*4882a593Smuzhiyun u32 data;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * PCIPDR may only be accessed as 32 bit words,
31*4882a593Smuzhiyun * so we must do byte alignment by hand
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun raw_spin_lock_irqsave(&pci_config_lock, flags);
34*4882a593Smuzhiyun pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
35*4882a593Smuzhiyun data = pci_read_reg(chan, SH4_PCIPDR);
36*4882a593Smuzhiyun raw_spin_unlock_irqrestore(&pci_config_lock, flags);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun switch (size) {
39*4882a593Smuzhiyun case 1:
40*4882a593Smuzhiyun *val = (data >> ((where & 3) << 3)) & 0xff;
41*4882a593Smuzhiyun break;
42*4882a593Smuzhiyun case 2:
43*4882a593Smuzhiyun *val = (data >> ((where & 2) << 3)) & 0xffff;
44*4882a593Smuzhiyun break;
45*4882a593Smuzhiyun case 4:
46*4882a593Smuzhiyun *val = data;
47*4882a593Smuzhiyun break;
48*4882a593Smuzhiyun default:
49*4882a593Smuzhiyun return PCIBIOS_FUNC_NOT_SUPPORTED;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * Since SH4 only does 32bit access we'll have to do a read,
57*4882a593Smuzhiyun * mask,write operation.
58*4882a593Smuzhiyun * We'll allow an odd byte offset, though it should be illegal.
59*4882a593Smuzhiyun */
sh4_pci_write(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)60*4882a593Smuzhiyun static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
61*4882a593Smuzhiyun int where, int size, u32 val)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun struct pci_channel *chan = bus->sysdata;
64*4882a593Smuzhiyun unsigned long flags;
65*4882a593Smuzhiyun int shift;
66*4882a593Smuzhiyun u32 data;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun raw_spin_lock_irqsave(&pci_config_lock, flags);
69*4882a593Smuzhiyun pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
70*4882a593Smuzhiyun data = pci_read_reg(chan, SH4_PCIPDR);
71*4882a593Smuzhiyun raw_spin_unlock_irqrestore(&pci_config_lock, flags);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun switch (size) {
74*4882a593Smuzhiyun case 1:
75*4882a593Smuzhiyun shift = (where & 3) << 3;
76*4882a593Smuzhiyun data &= ~(0xff << shift);
77*4882a593Smuzhiyun data |= ((val & 0xff) << shift);
78*4882a593Smuzhiyun break;
79*4882a593Smuzhiyun case 2:
80*4882a593Smuzhiyun shift = (where & 2) << 3;
81*4882a593Smuzhiyun data &= ~(0xffff << shift);
82*4882a593Smuzhiyun data |= ((val & 0xffff) << shift);
83*4882a593Smuzhiyun break;
84*4882a593Smuzhiyun case 4:
85*4882a593Smuzhiyun data = val;
86*4882a593Smuzhiyun break;
87*4882a593Smuzhiyun default:
88*4882a593Smuzhiyun return PCIBIOS_FUNC_NOT_SUPPORTED;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun pci_write_reg(chan, data, SH4_PCIPDR);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun struct pci_ops sh4_pci_ops = {
97*4882a593Smuzhiyun .read = sh4_pci_read,
98*4882a593Smuzhiyun .write = sh4_pci_write,
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
pci_fixup_pcic(struct pci_channel * chan)101*4882a593Smuzhiyun int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun /* Nothing to do. */
104*4882a593Smuzhiyun return 0;
105*4882a593Smuzhiyun }
106