1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/sh/drivers/pci/fixups-rts7751r2d.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * RTS7751R2D / LBOXRE2 PCI fixups
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2003 Lineo uSolutions, Inc.
8*4882a593Smuzhiyun * Copyright (C) 2004 Paul Mundt
9*4882a593Smuzhiyun * Copyright (C) 2007 Nobuhiro Iwamatsu
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun #include <linux/pci.h>
12*4882a593Smuzhiyun #include <mach/lboxre2.h>
13*4882a593Smuzhiyun #include <mach/r2d.h>
14*4882a593Smuzhiyun #include "pci-sh4.h"
15*4882a593Smuzhiyun #include <generated/machtypes.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define PCIMCR_MRSET_OFF 0xBFFFFFFF
18*4882a593Smuzhiyun #define PCIMCR_RFSH_OFF 0xFFFFFFFB
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static u8 rts7751r2d_irq_tab[] = {
21*4882a593Smuzhiyun IRQ_PCI_INTA,
22*4882a593Smuzhiyun IRQ_PCI_INTB,
23*4882a593Smuzhiyun IRQ_PCI_INTC,
24*4882a593Smuzhiyun IRQ_PCI_INTD,
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static char lboxre2_irq_tab[] = {
28*4882a593Smuzhiyun IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
pcibios_map_platform_irq(const struct pci_dev * pdev,u8 slot,u8 pin)31*4882a593Smuzhiyun int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun if (mach_is_lboxre2())
34*4882a593Smuzhiyun return lboxre2_irq_tab[slot];
35*4882a593Smuzhiyun else
36*4882a593Smuzhiyun return rts7751r2d_irq_tab[slot];
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
pci_fixup_pcic(struct pci_channel * chan)39*4882a593Smuzhiyun int pci_fixup_pcic(struct pci_channel *chan)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun unsigned long bcr1, mcr;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun bcr1 = __raw_readl(SH7751_BCR1);
44*4882a593Smuzhiyun bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
45*4882a593Smuzhiyun pci_write_reg(chan, bcr1, SH4_PCIBCR1);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* Enable all interrupts, so we known what to fix */
48*4882a593Smuzhiyun pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
49*4882a593Smuzhiyun pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
52*4882a593Smuzhiyun pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun mcr = __raw_readl(SH7751_MCR);
55*4882a593Smuzhiyun mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
56*4882a593Smuzhiyun pci_write_reg(chan, mcr, SH4_PCIMCR);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
59*4882a593Smuzhiyun pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
60*4882a593Smuzhiyun pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
61*4882a593Smuzhiyun pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return 0;
64*4882a593Smuzhiyun }
65