1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun #include <linux/pci.h>
3*4882a593Smuzhiyun #include <linux/interrupt.h>
4*4882a593Smuzhiyun #include <linux/timer.h>
5*4882a593Smuzhiyun #include <linux/kernel.h>
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun /*
8*4882a593Smuzhiyun * These functions are used early on before PCI scanning is done
9*4882a593Smuzhiyun * and all of the pci_dev and pci_bus structures have been created.
10*4882a593Smuzhiyun */
fake_pci_dev(struct pci_channel * hose,int top_bus,int busnr,int devfn)11*4882a593Smuzhiyun static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
12*4882a593Smuzhiyun int top_bus, int busnr, int devfn)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun static struct pci_dev dev;
15*4882a593Smuzhiyun static struct pci_bus bus;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun dev.bus = &bus;
18*4882a593Smuzhiyun dev.sysdata = hose;
19*4882a593Smuzhiyun dev.devfn = devfn;
20*4882a593Smuzhiyun bus.number = busnr;
21*4882a593Smuzhiyun bus.sysdata = hose;
22*4882a593Smuzhiyun bus.ops = hose->pci_ops;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun if(busnr != top_bus)
25*4882a593Smuzhiyun /* Fake a parent bus structure. */
26*4882a593Smuzhiyun bus.parent = &bus;
27*4882a593Smuzhiyun else
28*4882a593Smuzhiyun bus.parent = NULL;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun return &dev;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define EARLY_PCI_OP(rw, size, type) \
34*4882a593Smuzhiyun int __init early_##rw##_config_##size(struct pci_channel *hose, \
35*4882a593Smuzhiyun int top_bus, int bus, int devfn, int offset, type value) \
36*4882a593Smuzhiyun { \
37*4882a593Smuzhiyun return pci_##rw##_config_##size( \
38*4882a593Smuzhiyun fake_pci_dev(hose, top_bus, bus, devfn), \
39*4882a593Smuzhiyun offset, value); \
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
EARLY_PCI_OP(read,byte,u8 *)42*4882a593Smuzhiyun EARLY_PCI_OP(read, byte, u8 *)
43*4882a593Smuzhiyun EARLY_PCI_OP(read, word, u16 *)
44*4882a593Smuzhiyun EARLY_PCI_OP(read, dword, u32 *)
45*4882a593Smuzhiyun EARLY_PCI_OP(write, byte, u8)
46*4882a593Smuzhiyun EARLY_PCI_OP(write, word, u16)
47*4882a593Smuzhiyun EARLY_PCI_OP(write, dword, u32)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun int __init pci_is_66mhz_capable(struct pci_channel *hose,
50*4882a593Smuzhiyun int top_bus, int current_bus)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun u32 pci_devfn;
53*4882a593Smuzhiyun unsigned short vid;
54*4882a593Smuzhiyun int cap66 = -1;
55*4882a593Smuzhiyun u16 stat;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun pr_info("PCI: Checking 66MHz capabilities...\n");
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
60*4882a593Smuzhiyun if (PCI_FUNC(pci_devfn))
61*4882a593Smuzhiyun continue;
62*4882a593Smuzhiyun if (early_read_config_word(hose, top_bus, current_bus,
63*4882a593Smuzhiyun pci_devfn, PCI_VENDOR_ID, &vid) !=
64*4882a593Smuzhiyun PCIBIOS_SUCCESSFUL)
65*4882a593Smuzhiyun continue;
66*4882a593Smuzhiyun if (vid == 0xffff)
67*4882a593Smuzhiyun continue;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* check 66MHz capability */
70*4882a593Smuzhiyun if (cap66 < 0)
71*4882a593Smuzhiyun cap66 = 1;
72*4882a593Smuzhiyun if (cap66) {
73*4882a593Smuzhiyun early_read_config_word(hose, top_bus, current_bus,
74*4882a593Smuzhiyun pci_devfn, PCI_STATUS, &stat);
75*4882a593Smuzhiyun if (!(stat & PCI_STATUS_66MHZ)) {
76*4882a593Smuzhiyun printk(KERN_DEBUG
77*4882a593Smuzhiyun "PCI: %02x:%02x not 66MHz capable.\n",
78*4882a593Smuzhiyun current_bus, pci_devfn);
79*4882a593Smuzhiyun cap66 = 0;
80*4882a593Smuzhiyun break;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return cap66 > 0;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
pcibios_enable_err(struct timer_list * t)88*4882a593Smuzhiyun static void pcibios_enable_err(struct timer_list *t)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun struct pci_channel *hose = from_timer(hose, t, err_timer);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun del_timer(&hose->err_timer);
93*4882a593Smuzhiyun printk(KERN_DEBUG "PCI: re-enabling error IRQ.\n");
94*4882a593Smuzhiyun enable_irq(hose->err_irq);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
pcibios_enable_serr(struct timer_list * t)97*4882a593Smuzhiyun static void pcibios_enable_serr(struct timer_list *t)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun struct pci_channel *hose = from_timer(hose, t, serr_timer);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun del_timer(&hose->serr_timer);
102*4882a593Smuzhiyun printk(KERN_DEBUG "PCI: re-enabling system error IRQ.\n");
103*4882a593Smuzhiyun enable_irq(hose->serr_irq);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
pcibios_enable_timers(struct pci_channel * hose)106*4882a593Smuzhiyun void pcibios_enable_timers(struct pci_channel *hose)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun if (hose->err_irq) {
109*4882a593Smuzhiyun timer_setup(&hose->err_timer, pcibios_enable_err, 0);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun if (hose->serr_irq) {
113*4882a593Smuzhiyun timer_setup(&hose->serr_timer, pcibios_enable_serr, 0);
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /*
118*4882a593Smuzhiyun * A simple handler for the regular PCI status errors, called from IRQ
119*4882a593Smuzhiyun * context.
120*4882a593Smuzhiyun */
pcibios_handle_status_errors(unsigned long addr,unsigned int status,struct pci_channel * hose)121*4882a593Smuzhiyun unsigned int pcibios_handle_status_errors(unsigned long addr,
122*4882a593Smuzhiyun unsigned int status,
123*4882a593Smuzhiyun struct pci_channel *hose)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun unsigned int cmd = 0;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun if (status & PCI_STATUS_REC_MASTER_ABORT) {
128*4882a593Smuzhiyun printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n", addr);
129*4882a593Smuzhiyun cmd |= PCI_STATUS_REC_MASTER_ABORT;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun if (status & PCI_STATUS_REC_TARGET_ABORT) {
133*4882a593Smuzhiyun printk(KERN_DEBUG "PCI: target abort: ");
134*4882a593Smuzhiyun pcibios_report_status(PCI_STATUS_REC_TARGET_ABORT |
135*4882a593Smuzhiyun PCI_STATUS_SIG_TARGET_ABORT |
136*4882a593Smuzhiyun PCI_STATUS_REC_MASTER_ABORT, 1);
137*4882a593Smuzhiyun pr_cont("\n");
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun cmd |= PCI_STATUS_REC_TARGET_ABORT;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun if (status & (PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY)) {
143*4882a593Smuzhiyun printk(KERN_DEBUG "PCI: parity error detected: ");
144*4882a593Smuzhiyun pcibios_report_status(PCI_STATUS_PARITY |
145*4882a593Smuzhiyun PCI_STATUS_DETECTED_PARITY, 1);
146*4882a593Smuzhiyun pr_cont("\n");
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun cmd |= PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* Now back off of the IRQ for awhile */
151*4882a593Smuzhiyun if (hose->err_irq) {
152*4882a593Smuzhiyun disable_irq_nosync(hose->err_irq);
153*4882a593Smuzhiyun hose->err_timer.expires = jiffies + HZ;
154*4882a593Smuzhiyun add_timer(&hose->err_timer);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun return cmd;
159*4882a593Smuzhiyun }
160