1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/sh/drivers/dma/dma-pvr2.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * NEC PowerVR 2 (Dreamcast) DMA support
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2003, 2004 Paul Mundt
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <mach/sysasic.h>
14*4882a593Smuzhiyun #include <mach/dma.h>
15*4882a593Smuzhiyun #include <asm/dma.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static unsigned int xfer_complete;
19*4882a593Smuzhiyun static int count;
20*4882a593Smuzhiyun
pvr2_dma_interrupt(int irq,void * dev_id)21*4882a593Smuzhiyun static irqreturn_t pvr2_dma_interrupt(int irq, void *dev_id)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun if (get_dma_residue(PVR2_CASCADE_CHAN)) {
24*4882a593Smuzhiyun printk(KERN_WARNING "DMA: SH DMAC did not complete transfer "
25*4882a593Smuzhiyun "on channel %d, waiting..\n", PVR2_CASCADE_CHAN);
26*4882a593Smuzhiyun dma_wait_for_completion(PVR2_CASCADE_CHAN);
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun if (count++ < 10)
30*4882a593Smuzhiyun pr_debug("Got a pvr2 dma interrupt for channel %d\n",
31*4882a593Smuzhiyun irq - HW_EVENT_PVR2_DMA);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun xfer_complete = 1;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return IRQ_HANDLED;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
pvr2_request_dma(struct dma_channel * chan)38*4882a593Smuzhiyun static int pvr2_request_dma(struct dma_channel *chan)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun if (__raw_readl(PVR2_DMA_MODE) != 0)
41*4882a593Smuzhiyun return -EBUSY;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun __raw_writel(0, PVR2_DMA_LMMODE0);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun return 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
pvr2_get_dma_residue(struct dma_channel * chan)48*4882a593Smuzhiyun static int pvr2_get_dma_residue(struct dma_channel *chan)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun return xfer_complete == 0;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
pvr2_xfer_dma(struct dma_channel * chan)53*4882a593Smuzhiyun static int pvr2_xfer_dma(struct dma_channel *chan)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun if (chan->sar || !chan->dar)
56*4882a593Smuzhiyun return -EINVAL;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun xfer_complete = 0;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun __raw_writel(chan->dar, PVR2_DMA_ADDR);
61*4882a593Smuzhiyun __raw_writel(chan->count, PVR2_DMA_COUNT);
62*4882a593Smuzhiyun __raw_writel(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return 0;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static struct dma_ops pvr2_dma_ops = {
68*4882a593Smuzhiyun .request = pvr2_request_dma,
69*4882a593Smuzhiyun .get_residue = pvr2_get_dma_residue,
70*4882a593Smuzhiyun .xfer = pvr2_xfer_dma,
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static struct dma_info pvr2_dma_info = {
74*4882a593Smuzhiyun .name = "pvr2_dmac",
75*4882a593Smuzhiyun .nr_channels = 1,
76*4882a593Smuzhiyun .ops = &pvr2_dma_ops,
77*4882a593Smuzhiyun .flags = DMAC_CHANNELS_TEI_CAPABLE,
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
pvr2_dma_init(void)80*4882a593Smuzhiyun static int __init pvr2_dma_init(void)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun if (request_irq(HW_EVENT_PVR2_DMA, pvr2_dma_interrupt, 0,
83*4882a593Smuzhiyun "pvr2 DMA handler", NULL))
84*4882a593Smuzhiyun pr_err("Failed to register pvr2 DMA handler interrupt\n");
85*4882a593Smuzhiyun request_dma(PVR2_CASCADE_CHAN, "pvr2 cascade");
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return register_dmac(&pvr2_dma_info);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
pvr2_dma_exit(void)90*4882a593Smuzhiyun static void __exit pvr2_dma_exit(void)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun free_dma(PVR2_CASCADE_CHAN);
93*4882a593Smuzhiyun free_irq(HW_EVENT_PVR2_DMA, 0);
94*4882a593Smuzhiyun unregister_dmac(&pvr2_dma_info);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun subsys_initcall(pvr2_dma_init);
98*4882a593Smuzhiyun module_exit(pvr2_dma_exit);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
101*4882a593Smuzhiyun MODULE_DESCRIPTION("NEC PowerVR 2 DMA driver");
102*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
103