1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/sh/drivers/dma/dma-g2.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * G2 bus DMA support
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2003 - 2006 Paul Mundt
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <asm/cacheflush.h>
14*4882a593Smuzhiyun #include <mach/sysasic.h>
15*4882a593Smuzhiyun #include <mach/dma.h>
16*4882a593Smuzhiyun #include <asm/dma.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct g2_channel {
19*4882a593Smuzhiyun unsigned long g2_addr; /* G2 bus address */
20*4882a593Smuzhiyun unsigned long root_addr; /* Root bus (SH-4) address */
21*4882a593Smuzhiyun unsigned long size; /* Size (in bytes), 32-byte aligned */
22*4882a593Smuzhiyun unsigned long direction; /* Transfer direction */
23*4882a593Smuzhiyun unsigned long ctrl; /* Transfer control */
24*4882a593Smuzhiyun unsigned long chan_enable; /* Channel enable */
25*4882a593Smuzhiyun unsigned long xfer_enable; /* Transfer enable */
26*4882a593Smuzhiyun unsigned long xfer_stat; /* Transfer status */
27*4882a593Smuzhiyun } __attribute__ ((aligned(32)));
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct g2_status {
30*4882a593Smuzhiyun unsigned long g2_addr;
31*4882a593Smuzhiyun unsigned long root_addr;
32*4882a593Smuzhiyun unsigned long size;
33*4882a593Smuzhiyun unsigned long status;
34*4882a593Smuzhiyun } __attribute__ ((aligned(16)));
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun struct g2_dma_info {
37*4882a593Smuzhiyun struct g2_channel channel[G2_NR_DMA_CHANNELS];
38*4882a593Smuzhiyun unsigned long pad1[G2_NR_DMA_CHANNELS];
39*4882a593Smuzhiyun unsigned long wait_state;
40*4882a593Smuzhiyun unsigned long pad2[10];
41*4882a593Smuzhiyun unsigned long magic;
42*4882a593Smuzhiyun struct g2_status status[G2_NR_DMA_CHANNELS];
43*4882a593Smuzhiyun } __attribute__ ((aligned(256)));
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static volatile struct g2_dma_info *g2_dma = (volatile struct g2_dma_info *)0xa05f7800;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define g2_bytes_remaining(i) \
48*4882a593Smuzhiyun ((g2_dma->channel[i].size - \
49*4882a593Smuzhiyun g2_dma->status[i].size) & 0x0fffffff)
50*4882a593Smuzhiyun
g2_dma_interrupt(int irq,void * dev_id)51*4882a593Smuzhiyun static irqreturn_t g2_dma_interrupt(int irq, void *dev_id)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun int i;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun for (i = 0; i < G2_NR_DMA_CHANNELS; i++) {
56*4882a593Smuzhiyun if (g2_dma->status[i].status & 0x20000000) {
57*4882a593Smuzhiyun unsigned int bytes = g2_bytes_remaining(i);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun if (likely(bytes == 0)) {
60*4882a593Smuzhiyun struct dma_info *info = dev_id;
61*4882a593Smuzhiyun struct dma_channel *chan = info->channels + i;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun wake_up(&chan->wait_queue);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return IRQ_HANDLED;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun return IRQ_NONE;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
g2_enable_dma(struct dma_channel * chan)73*4882a593Smuzhiyun static int g2_enable_dma(struct dma_channel *chan)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun unsigned int chan_nr = chan->chan;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun g2_dma->channel[chan_nr].chan_enable = 1;
78*4882a593Smuzhiyun g2_dma->channel[chan_nr].xfer_enable = 1;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return 0;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
g2_disable_dma(struct dma_channel * chan)83*4882a593Smuzhiyun static int g2_disable_dma(struct dma_channel *chan)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun unsigned int chan_nr = chan->chan;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun g2_dma->channel[chan_nr].chan_enable = 0;
88*4882a593Smuzhiyun g2_dma->channel[chan_nr].xfer_enable = 0;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun return 0;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
g2_xfer_dma(struct dma_channel * chan)93*4882a593Smuzhiyun static int g2_xfer_dma(struct dma_channel *chan)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun unsigned int chan_nr = chan->chan;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (chan->sar & 31) {
98*4882a593Smuzhiyun printk("g2dma: unaligned source 0x%lx\n", chan->sar);
99*4882a593Smuzhiyun return -EINVAL;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun if (chan->dar & 31) {
103*4882a593Smuzhiyun printk("g2dma: unaligned dest 0x%lx\n", chan->dar);
104*4882a593Smuzhiyun return -EINVAL;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* Align the count */
108*4882a593Smuzhiyun if (chan->count & 31)
109*4882a593Smuzhiyun chan->count = (chan->count + (32 - 1)) & ~(32 - 1);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Fixup destination */
112*4882a593Smuzhiyun chan->dar += 0xa0800000;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Fixup direction */
115*4882a593Smuzhiyun chan->mode = !chan->mode;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun flush_icache_range((unsigned long)chan->sar, chan->count);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun g2_disable_dma(chan);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun g2_dma->channel[chan_nr].g2_addr = chan->dar & 0x1fffffe0;
122*4882a593Smuzhiyun g2_dma->channel[chan_nr].root_addr = chan->sar & 0x1fffffe0;
123*4882a593Smuzhiyun g2_dma->channel[chan_nr].size = (chan->count & ~31) | 0x80000000;
124*4882a593Smuzhiyun g2_dma->channel[chan_nr].direction = chan->mode;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /*
127*4882a593Smuzhiyun * bit 0 - ???
128*4882a593Smuzhiyun * bit 1 - if set, generate a hardware event on transfer completion
129*4882a593Smuzhiyun * bit 2 - ??? something to do with suspend?
130*4882a593Smuzhiyun */
131*4882a593Smuzhiyun g2_dma->channel[chan_nr].ctrl = 5; /* ?? */
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun g2_enable_dma(chan);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /* debug cruft */
136*4882a593Smuzhiyun pr_debug("count, sar, dar, mode, ctrl, chan, xfer: %ld, 0x%08lx, "
137*4882a593Smuzhiyun "0x%08lx, %ld, %ld, %ld, %ld\n",
138*4882a593Smuzhiyun g2_dma->channel[chan_nr].size,
139*4882a593Smuzhiyun g2_dma->channel[chan_nr].root_addr,
140*4882a593Smuzhiyun g2_dma->channel[chan_nr].g2_addr,
141*4882a593Smuzhiyun g2_dma->channel[chan_nr].direction,
142*4882a593Smuzhiyun g2_dma->channel[chan_nr].ctrl,
143*4882a593Smuzhiyun g2_dma->channel[chan_nr].chan_enable,
144*4882a593Smuzhiyun g2_dma->channel[chan_nr].xfer_enable);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun return 0;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
g2_get_residue(struct dma_channel * chan)149*4882a593Smuzhiyun static int g2_get_residue(struct dma_channel *chan)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun return g2_bytes_remaining(chan->chan);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun static struct dma_ops g2_dma_ops = {
155*4882a593Smuzhiyun .xfer = g2_xfer_dma,
156*4882a593Smuzhiyun .get_residue = g2_get_residue,
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun static struct dma_info g2_dma_info = {
160*4882a593Smuzhiyun .name = "g2_dmac",
161*4882a593Smuzhiyun .nr_channels = 4,
162*4882a593Smuzhiyun .ops = &g2_dma_ops,
163*4882a593Smuzhiyun .flags = DMAC_CHANNELS_TEI_CAPABLE,
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun
g2_dma_init(void)166*4882a593Smuzhiyun static int __init g2_dma_init(void)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun int ret;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun ret = request_irq(HW_EVENT_G2_DMA, g2_dma_interrupt, 0,
171*4882a593Smuzhiyun "g2 DMA handler", &g2_dma_info);
172*4882a593Smuzhiyun if (unlikely(ret))
173*4882a593Smuzhiyun return -EINVAL;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun /* Magic */
176*4882a593Smuzhiyun g2_dma->wait_state = 27;
177*4882a593Smuzhiyun g2_dma->magic = 0x4659404f;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun ret = register_dmac(&g2_dma_info);
180*4882a593Smuzhiyun if (unlikely(ret != 0))
181*4882a593Smuzhiyun free_irq(HW_EVENT_G2_DMA, &g2_dma_info);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun return ret;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
g2_dma_exit(void)186*4882a593Smuzhiyun static void __exit g2_dma_exit(void)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun free_irq(HW_EVENT_G2_DMA, &g2_dma_info);
189*4882a593Smuzhiyun unregister_dmac(&g2_dma_info);
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun subsys_initcall(g2_dma_init);
193*4882a593Smuzhiyun module_exit(g2_dma_exit);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
196*4882a593Smuzhiyun MODULE_DESCRIPTION("G2 bus DMA driver");
197*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
198