1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2000 YAEGASHI Takeshi
4*4882a593Smuzhiyun * Hitachi HD64461 companion chip support
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/sched.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/param.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/irq.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <asm/irq.h>
16*4882a593Smuzhiyun #include <asm/hd64461.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* This belongs in cpu specific */
19*4882a593Smuzhiyun #define INTC_ICR1 0xA4140010UL
20*4882a593Smuzhiyun
hd64461_mask_irq(struct irq_data * data)21*4882a593Smuzhiyun static void hd64461_mask_irq(struct irq_data *data)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun unsigned int irq = data->irq;
24*4882a593Smuzhiyun unsigned short nimr;
25*4882a593Smuzhiyun unsigned short mask = 1 << (irq - HD64461_IRQBASE);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun nimr = __raw_readw(HD64461_NIMR);
28*4882a593Smuzhiyun nimr |= mask;
29*4882a593Smuzhiyun __raw_writew(nimr, HD64461_NIMR);
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
hd64461_unmask_irq(struct irq_data * data)32*4882a593Smuzhiyun static void hd64461_unmask_irq(struct irq_data *data)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun unsigned int irq = data->irq;
35*4882a593Smuzhiyun unsigned short nimr;
36*4882a593Smuzhiyun unsigned short mask = 1 << (irq - HD64461_IRQBASE);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun nimr = __raw_readw(HD64461_NIMR);
39*4882a593Smuzhiyun nimr &= ~mask;
40*4882a593Smuzhiyun __raw_writew(nimr, HD64461_NIMR);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
hd64461_mask_and_ack_irq(struct irq_data * data)43*4882a593Smuzhiyun static void hd64461_mask_and_ack_irq(struct irq_data *data)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun hd64461_mask_irq(data);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #ifdef CONFIG_HD64461_ENABLER
48*4882a593Smuzhiyun if (data->irq == HD64461_IRQBASE + 13)
49*4882a593Smuzhiyun __raw_writeb(0x00, HD64461_PCC1CSCR);
50*4882a593Smuzhiyun #endif
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static struct irq_chip hd64461_irq_chip = {
54*4882a593Smuzhiyun .name = "HD64461-IRQ",
55*4882a593Smuzhiyun .irq_mask = hd64461_mask_irq,
56*4882a593Smuzhiyun .irq_mask_ack = hd64461_mask_and_ack_irq,
57*4882a593Smuzhiyun .irq_unmask = hd64461_unmask_irq,
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
hd64461_irq_demux(struct irq_desc * desc)60*4882a593Smuzhiyun static void hd64461_irq_demux(struct irq_desc *desc)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun unsigned short intv = __raw_readw(HD64461_NIRR);
63*4882a593Smuzhiyun unsigned int ext_irq = HD64461_IRQBASE;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun intv &= (1 << HD64461_IRQ_NUM) - 1;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun for (; intv; intv >>= 1, ext_irq++) {
68*4882a593Smuzhiyun if (!(intv & 1))
69*4882a593Smuzhiyun continue;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun generic_handle_irq(ext_irq);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
setup_hd64461(void)75*4882a593Smuzhiyun int __init setup_hd64461(void)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun int irq_base, i;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun printk(KERN_INFO
80*4882a593Smuzhiyun "HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n",
81*4882a593Smuzhiyun HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE,
82*4882a593Smuzhiyun HD64461_IRQBASE + 15);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Should be at processor specific part.. */
85*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7709)
86*4882a593Smuzhiyun __raw_writew(0x2240, INTC_ICR1);
87*4882a593Smuzhiyun #endif
88*4882a593Smuzhiyun __raw_writew(0xffff, HD64461_NIMR);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun irq_base = irq_alloc_descs(HD64461_IRQBASE, HD64461_IRQBASE, 16, -1);
91*4882a593Smuzhiyun if (IS_ERR_VALUE(irq_base)) {
92*4882a593Smuzhiyun pr_err("%s: failed hooking irqs for HD64461\n", __func__);
93*4882a593Smuzhiyun return irq_base;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun for (i = 0; i < 16; i++)
97*4882a593Smuzhiyun irq_set_chip_and_handler(irq_base + i, &hd64461_irq_chip,
98*4882a593Smuzhiyun handle_level_irq);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
101*4882a593Smuzhiyun irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #ifdef CONFIG_HD64461_ENABLER
104*4882a593Smuzhiyun printk(KERN_INFO "HD64461: enabling PCMCIA devices\n");
105*4882a593Smuzhiyun __raw_writeb(0x4c, HD64461_PCC1CSCIER);
106*4882a593Smuzhiyun __raw_writeb(0x00, HD64461_PCC1CSCR);
107*4882a593Smuzhiyun #endif
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return 0;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun module_init(setup_hd64461);
113