1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * sh7724 MMCIF loader
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2010 Magnus Damm
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
7*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
8*4882a593Smuzhiyun * for more details.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/mmc/sh_mmcif.h>
12*4882a593Smuzhiyun #include <mach/romimage.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define MMCIF_BASE (void __iomem *)0xa4ca0000
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define MSTPCR2 0xa4150038
17*4882a593Smuzhiyun #define PTWCR 0xa4050146
18*4882a593Smuzhiyun #define PTXCR 0xa4050148
19*4882a593Smuzhiyun #define PSELA 0xa405014e
20*4882a593Smuzhiyun #define PSELE 0xa4050156
21*4882a593Smuzhiyun #define HIZCRC 0xa405015c
22*4882a593Smuzhiyun #define DRVCRA 0xa405018a
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun enum {
25*4882a593Smuzhiyun MMCIF_PROGRESS_ENTER,
26*4882a593Smuzhiyun MMCIF_PROGRESS_INIT,
27*4882a593Smuzhiyun MMCIF_PROGRESS_LOAD,
28*4882a593Smuzhiyun MMCIF_PROGRESS_DONE
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* SH7724 specific MMCIF loader
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun * loads the romImage from an MMC card starting from block 512
34*4882a593Smuzhiyun * use the following line to write the romImage to an MMC card
35*4882a593Smuzhiyun * # dd if=arch/sh/boot/romImage of=/dev/sdx bs=512 seek=512
36*4882a593Smuzhiyun */
mmcif_loader(unsigned char * buf,unsigned long no_bytes)37*4882a593Smuzhiyun asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun mmcif_update_progress(MMCIF_PROGRESS_ENTER);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* enable clock to the MMCIF hardware block */
42*4882a593Smuzhiyun __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* setup pins D7-D0 */
45*4882a593Smuzhiyun __raw_writew(0x0000, PTWCR);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* setup pins MMC_CLK, MMC_CMD */
48*4882a593Smuzhiyun __raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* select D3-D0 pin function */
51*4882a593Smuzhiyun __raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* select D7-D4 pin function */
54*4882a593Smuzhiyun __raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* disable Hi-Z for the MMC pins */
57*4882a593Smuzhiyun __raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* high drive capability for MMC pins */
60*4882a593Smuzhiyun __raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun mmcif_update_progress(MMCIF_PROGRESS_INIT);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* setup MMCIF hardware */
65*4882a593Smuzhiyun sh_mmcif_boot_init(MMCIF_BASE);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun mmcif_update_progress(MMCIF_PROGRESS_LOAD);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* load kernel via MMCIF interface */
70*4882a593Smuzhiyun sh_mmcif_boot_do_read(MMCIF_BASE, 512,
71*4882a593Smuzhiyun (no_bytes + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS,
72*4882a593Smuzhiyun buf);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* disable clock to the MMCIF hardware block */
75*4882a593Smuzhiyun __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun mmcif_update_progress(MMCIF_PROGRESS_DONE);
78*4882a593Smuzhiyun }
79