xref: /OK3568_Linux_fs/kernel/arch/sh/boards/of-generic.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * SH generic board support, using device tree
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/of.h>
9*4882a593Smuzhiyun #include <linux/of_fdt.h>
10*4882a593Smuzhiyun #include <linux/clocksource.h>
11*4882a593Smuzhiyun #include <linux/irqchip.h>
12*4882a593Smuzhiyun #include <linux/clk-provider.h>
13*4882a593Smuzhiyun #include <asm/machvec.h>
14*4882a593Smuzhiyun #include <asm/rtc.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #ifdef CONFIG_SMP
17*4882a593Smuzhiyun 
dummy_smp_setup(void)18*4882a593Smuzhiyun static void dummy_smp_setup(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun }
21*4882a593Smuzhiyun 
dummy_prepare_cpus(unsigned int max_cpus)22*4882a593Smuzhiyun static void dummy_prepare_cpus(unsigned int max_cpus)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun }
25*4882a593Smuzhiyun 
dummy_start_cpu(unsigned int cpu,unsigned long entry_point)26*4882a593Smuzhiyun static void dummy_start_cpu(unsigned int cpu, unsigned long entry_point)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun 
dummy_smp_processor_id(void)30*4882a593Smuzhiyun static unsigned int dummy_smp_processor_id(void)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun 	return 0;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun 
dummy_send_ipi(unsigned int cpu,unsigned int message)35*4882a593Smuzhiyun static void dummy_send_ipi(unsigned int cpu, unsigned int message)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun static struct plat_smp_ops dummy_smp_ops = {
40*4882a593Smuzhiyun 	.smp_setup		= dummy_smp_setup,
41*4882a593Smuzhiyun 	.prepare_cpus		= dummy_prepare_cpus,
42*4882a593Smuzhiyun 	.start_cpu		= dummy_start_cpu,
43*4882a593Smuzhiyun 	.smp_processor_id	= dummy_smp_processor_id,
44*4882a593Smuzhiyun 	.send_ipi		= dummy_send_ipi,
45*4882a593Smuzhiyun 	.cpu_die		= native_cpu_die,
46*4882a593Smuzhiyun 	.cpu_disable		= native_cpu_disable,
47*4882a593Smuzhiyun 	.play_dead		= native_play_dead,
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun extern const struct of_cpu_method __cpu_method_of_table[];
51*4882a593Smuzhiyun const struct of_cpu_method __cpu_method_of_table_sentinel
52*4882a593Smuzhiyun 	__section("__cpu_method_of_table_end");
53*4882a593Smuzhiyun 
sh_of_smp_probe(void)54*4882a593Smuzhiyun static void sh_of_smp_probe(void)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun 	struct device_node *np;
57*4882a593Smuzhiyun 	const char *method = NULL;
58*4882a593Smuzhiyun 	const struct of_cpu_method *m = __cpu_method_of_table;
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	pr_info("SH generic board support: scanning for cpus\n");
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	init_cpu_possible(cpumask_of(0));
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	for_each_of_cpu_node(np) {
65*4882a593Smuzhiyun 		const __be32 *cell = of_get_property(np, "reg", NULL);
66*4882a593Smuzhiyun 		u64 id = -1;
67*4882a593Smuzhiyun 		if (cell) id = of_read_number(cell, of_n_addr_cells(np));
68*4882a593Smuzhiyun 		if (id < NR_CPUS) {
69*4882a593Smuzhiyun 			if (!method)
70*4882a593Smuzhiyun 				of_property_read_string(np, "enable-method", &method);
71*4882a593Smuzhiyun 			set_cpu_possible(id, true);
72*4882a593Smuzhiyun 			set_cpu_present(id, true);
73*4882a593Smuzhiyun 			__cpu_number_map[id] = id;
74*4882a593Smuzhiyun 			__cpu_logical_map[id] = id;
75*4882a593Smuzhiyun 		}
76*4882a593Smuzhiyun 	}
77*4882a593Smuzhiyun 	if (!method) {
78*4882a593Smuzhiyun 		np = of_find_node_by_name(NULL, "cpus");
79*4882a593Smuzhiyun 		of_property_read_string(np, "enable-method", &method);
80*4882a593Smuzhiyun 		of_node_put(np);
81*4882a593Smuzhiyun 	}
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	pr_info("CPU enable method: %s\n", method);
84*4882a593Smuzhiyun 	if (method)
85*4882a593Smuzhiyun 		for (; m->method; m++)
86*4882a593Smuzhiyun 			if (!strcmp(m->method, method)) {
87*4882a593Smuzhiyun 				register_smp_ops(m->ops);
88*4882a593Smuzhiyun 				return;
89*4882a593Smuzhiyun 			}
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	register_smp_ops(&dummy_smp_ops);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #else
95*4882a593Smuzhiyun 
sh_of_smp_probe(void)96*4882a593Smuzhiyun static void sh_of_smp_probe(void)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun #endif
101*4882a593Smuzhiyun 
noop(void)102*4882a593Smuzhiyun static void noop(void)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
noopi(void)106*4882a593Smuzhiyun static int noopi(void)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun 	return 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun 
sh_of_mem_reserve(void)111*4882a593Smuzhiyun static void __init sh_of_mem_reserve(void)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun 	early_init_fdt_reserve_self();
114*4882a593Smuzhiyun 	early_init_fdt_scan_reserved_mem();
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun 
sh_of_setup(char ** cmdline_p)117*4882a593Smuzhiyun static void __init sh_of_setup(char **cmdline_p)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	struct device_node *root;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	sh_mv.mv_name = "Unknown SH model";
122*4882a593Smuzhiyun 	root = of_find_node_by_path("/");
123*4882a593Smuzhiyun 	if (root) {
124*4882a593Smuzhiyun 		of_property_read_string(root, "model", &sh_mv.mv_name);
125*4882a593Smuzhiyun 		of_node_put(root);
126*4882a593Smuzhiyun 	}
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	sh_of_smp_probe();
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
sh_of_irq_demux(int irq)131*4882a593Smuzhiyun static int sh_of_irq_demux(int irq)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	/* FIXME: eventually this should not be used at all;
134*4882a593Smuzhiyun 	 * the interrupt controller should set_handle_irq(). */
135*4882a593Smuzhiyun 	return irq;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun 
sh_of_init_irq(void)138*4882a593Smuzhiyun static void __init sh_of_init_irq(void)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun 	pr_info("SH generic board support: scanning for interrupt controllers\n");
141*4882a593Smuzhiyun 	irqchip_init();
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun 
sh_of_clk_init(void)144*4882a593Smuzhiyun static int __init sh_of_clk_init(void)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun #ifdef CONFIG_COMMON_CLK
147*4882a593Smuzhiyun 	/* Disabled pending move to COMMON_CLK framework. */
148*4882a593Smuzhiyun 	pr_info("SH generic board support: scanning for clk providers\n");
149*4882a593Smuzhiyun 	of_clk_init(NULL);
150*4882a593Smuzhiyun #endif
151*4882a593Smuzhiyun 	return 0;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun static struct sh_machine_vector __initmv sh_of_generic_mv = {
155*4882a593Smuzhiyun 	.mv_setup	= sh_of_setup,
156*4882a593Smuzhiyun 	.mv_name	= "devicetree", /* replaced by DT root's model */
157*4882a593Smuzhiyun 	.mv_irq_demux	= sh_of_irq_demux,
158*4882a593Smuzhiyun 	.mv_init_irq	= sh_of_init_irq,
159*4882a593Smuzhiyun 	.mv_clk_init	= sh_of_clk_init,
160*4882a593Smuzhiyun 	.mv_mode_pins	= noopi,
161*4882a593Smuzhiyun 	.mv_mem_init	= noop,
162*4882a593Smuzhiyun 	.mv_mem_reserve	= sh_of_mem_reserve,
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun struct sh_clk_ops;
166*4882a593Smuzhiyun 
arch_init_clk_ops(struct sh_clk_ops ** ops,int idx)167*4882a593Smuzhiyun void __init __weak arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun 
plat_irq_setup(void)171*4882a593Smuzhiyun void __init __weak plat_irq_setup(void)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun }
174