1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/arch/sh/boards/se/7780/irq.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2006,2007 Nobuhiro Iwamatsu
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Hitachi UL SolutionEngine 7780 Support.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/irq.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <mach-se/mach/se7780.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define INTC_BASE 0xffd00000
16*4882a593Smuzhiyun #define INTC_ICR1 (INTC_BASE+0x1c)
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun * Initialize IRQ setting
20*4882a593Smuzhiyun */
init_se7780_IRQ(void)21*4882a593Smuzhiyun void __init init_se7780_IRQ(void)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun /* enable all interrupt at FPGA */
24*4882a593Smuzhiyun __raw_writew(0, FPGA_INTMSK1);
25*4882a593Smuzhiyun /* mask SM501 interrupt */
26*4882a593Smuzhiyun __raw_writew((__raw_readw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
27*4882a593Smuzhiyun /* enable all interrupt at FPGA */
28*4882a593Smuzhiyun __raw_writew(0, FPGA_INTMSK2);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* set FPGA INTSEL register */
31*4882a593Smuzhiyun /* FPGA + 0x06 */
32*4882a593Smuzhiyun __raw_writew( ((IRQPIN_SM501 << IRQPOS_SM501) |
33*4882a593Smuzhiyun (IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* FPGA + 0x08 */
36*4882a593Smuzhiyun __raw_writew(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
37*4882a593Smuzhiyun (IRQPIN_EXTINT3 << IRQPOS_EXTINT3) |
38*4882a593Smuzhiyun (IRQPIN_EXTINT2 << IRQPOS_EXTINT2) |
39*4882a593Smuzhiyun (IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* FPGA + 0x0A */
42*4882a593Smuzhiyun __raw_writew((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* ICR1: detect low level(for 2ndcut) */
47*4882a593Smuzhiyun __raw_writel(0xAAAA0000, INTC_ICR1);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /*
50*4882a593Smuzhiyun * FPGA PCISEL register initialize
51*4882a593Smuzhiyun *
52*4882a593Smuzhiyun * CPU || SLOT1 | SLOT2 | S-ATA | USB
53*4882a593Smuzhiyun * -------------------------------------
54*4882a593Smuzhiyun * INTA || INTA | INTD | -- | INTB
55*4882a593Smuzhiyun * -------------------------------------
56*4882a593Smuzhiyun * INTB || INTB | INTA | -- | INTC
57*4882a593Smuzhiyun * -------------------------------------
58*4882a593Smuzhiyun * INTC || INTC | INTB | INTA | --
59*4882a593Smuzhiyun * -------------------------------------
60*4882a593Smuzhiyun * INTD || INTD | INTC | -- | INTA
61*4882a593Smuzhiyun * -------------------------------------
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun __raw_writew(0x0013, FPGA_PCI_INTSEL1);
64*4882a593Smuzhiyun __raw_writew(0xE402, FPGA_PCI_INTSEL2);
65*4882a593Smuzhiyun }
66