1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Hitachi UL SolutionEngine 7722 FPGA IRQ Support.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2007 Nobuhiro Iwamatsu
6*4882a593Smuzhiyun * Copyright (C) 2012 Paul Mundt
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #define DRV_NAME "SE7722-FPGA"
9*4882a593Smuzhiyun #define pr_fmt(fmt) DRV_NAME ": " fmt
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/irq.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/irqdomain.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/err.h>
17*4882a593Smuzhiyun #include <linux/sizes.h>
18*4882a593Smuzhiyun #include <mach-se/mach/se7722.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define IRQ01_BASE_ADDR 0x11800000
21*4882a593Smuzhiyun #define IRQ01_MODE_REG 0
22*4882a593Smuzhiyun #define IRQ01_STS_REG 4
23*4882a593Smuzhiyun #define IRQ01_MASK_REG 8
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static void __iomem *se7722_irq_regs;
26*4882a593Smuzhiyun struct irq_domain *se7722_irq_domain;
27*4882a593Smuzhiyun
se7722_irq_demux(struct irq_desc * desc)28*4882a593Smuzhiyun static void se7722_irq_demux(struct irq_desc *desc)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun struct irq_data *data = irq_desc_get_irq_data(desc);
31*4882a593Smuzhiyun struct irq_chip *chip = irq_data_get_irq_chip(data);
32*4882a593Smuzhiyun unsigned long mask;
33*4882a593Smuzhiyun int bit;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun chip->irq_mask_ack(data);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)
40*4882a593Smuzhiyun generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit));
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun chip->irq_unmask(data);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
se7722_domain_init(void)45*4882a593Smuzhiyun static void __init se7722_domain_init(void)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun int i;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR,
50*4882a593Smuzhiyun &irq_domain_simple_ops, NULL);
51*4882a593Smuzhiyun if (unlikely(!se7722_irq_domain)) {
52*4882a593Smuzhiyun printk("Failed to get IRQ domain\n");
53*4882a593Smuzhiyun return;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
57*4882a593Smuzhiyun int irq = irq_create_mapping(se7722_irq_domain, i);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun if (unlikely(irq == 0)) {
60*4882a593Smuzhiyun printk("Failed to allocate IRQ %d\n", i);
61*4882a593Smuzhiyun return;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
se7722_gc_init(void)66*4882a593Smuzhiyun static void __init se7722_gc_init(void)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct irq_chip_generic *gc;
69*4882a593Smuzhiyun struct irq_chip_type *ct;
70*4882a593Smuzhiyun unsigned int irq_base;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun irq_base = irq_linear_revmap(se7722_irq_domain, 0);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs,
75*4882a593Smuzhiyun handle_level_irq);
76*4882a593Smuzhiyun if (unlikely(!gc))
77*4882a593Smuzhiyun return;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun ct = gc->chip_types;
80*4882a593Smuzhiyun ct->chip.irq_mask = irq_gc_mask_set_bit;
81*4882a593Smuzhiyun ct->chip.irq_unmask = irq_gc_mask_clr_bit;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun ct->regs.mask = IRQ01_MASK_REG;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),
86*4882a593Smuzhiyun IRQ_GC_INIT_MASK_CACHE,
87*4882a593Smuzhiyun IRQ_NOREQUEST | IRQ_NOPROBE, 0);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
90*4882a593Smuzhiyun irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
93*4882a593Smuzhiyun irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /*
97*4882a593Smuzhiyun * Initialize FPGA IRQs
98*4882a593Smuzhiyun */
init_se7722_IRQ(void)99*4882a593Smuzhiyun void __init init_se7722_IRQ(void)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16);
102*4882a593Smuzhiyun if (unlikely(!se7722_irq_regs)) {
103*4882a593Smuzhiyun printk("Failed to remap IRQ01 regs\n");
104*4882a593Smuzhiyun return;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun * All FPGA IRQs disabled by default
109*4882a593Smuzhiyun */
110*4882a593Smuzhiyun iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun se7722_domain_init();
115*4882a593Smuzhiyun se7722_gc_init();
116*4882a593Smuzhiyun }
117