xref: /OK3568_Linux_fs/kernel/arch/sh/boards/mach-se/770x/setup.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * linux/arch/sh/boards/se/770x/setup.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2000  Kazumoto Kojima
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Hitachi SolutionEngine Support.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/sh_eth.h>
13*4882a593Smuzhiyun #include <mach-se/mach/se.h>
14*4882a593Smuzhiyun #include <mach-se/mach/mrshpc.h>
15*4882a593Smuzhiyun #include <asm/machvec.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include <asm/smc37c93x.h>
18*4882a593Smuzhiyun #include <asm/heartbeat.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun  * Configure the Super I/O chip
22*4882a593Smuzhiyun  */
smsc_config(int index,int data)23*4882a593Smuzhiyun static void __init smsc_config(int index, int data)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun 	outb_p(index, INDEX_PORT);
26*4882a593Smuzhiyun 	outb_p(data, DATA_PORT);
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /* XXX: Another candidate for a more generic cchip machine vector */
smsc_setup(char ** cmdline_p)30*4882a593Smuzhiyun static void __init smsc_setup(char **cmdline_p)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun 	outb_p(CONFIG_ENTER, CONFIG_PORT);
33*4882a593Smuzhiyun 	outb_p(CONFIG_ENTER, CONFIG_PORT);
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 	/* FDC */
36*4882a593Smuzhiyun 	smsc_config(CURRENT_LDN_INDEX, LDN_FDC);
37*4882a593Smuzhiyun 	smsc_config(ACTIVATE_INDEX, 0x01);
38*4882a593Smuzhiyun 	smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	/* AUXIO (GPIO): to use IDE1 */
41*4882a593Smuzhiyun 	smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO);
42*4882a593Smuzhiyun 	smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */
43*4882a593Smuzhiyun 	smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	/* COM1 */
46*4882a593Smuzhiyun 	smsc_config(CURRENT_LDN_INDEX, LDN_COM1);
47*4882a593Smuzhiyun 	smsc_config(ACTIVATE_INDEX, 0x01);
48*4882a593Smuzhiyun 	smsc_config(IO_BASE_HI_INDEX, 0x03);
49*4882a593Smuzhiyun 	smsc_config(IO_BASE_LO_INDEX, 0xf8);
50*4882a593Smuzhiyun 	smsc_config(IRQ_SELECT_INDEX, 4); /* IRQ4 */
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	/* COM2 */
53*4882a593Smuzhiyun 	smsc_config(CURRENT_LDN_INDEX, LDN_COM2);
54*4882a593Smuzhiyun 	smsc_config(ACTIVATE_INDEX, 0x01);
55*4882a593Smuzhiyun 	smsc_config(IO_BASE_HI_INDEX, 0x02);
56*4882a593Smuzhiyun 	smsc_config(IO_BASE_LO_INDEX, 0xf8);
57*4882a593Smuzhiyun 	smsc_config(IRQ_SELECT_INDEX, 3); /* IRQ3 */
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	/* RTC */
60*4882a593Smuzhiyun 	smsc_config(CURRENT_LDN_INDEX, LDN_RTC);
61*4882a593Smuzhiyun 	smsc_config(ACTIVATE_INDEX, 0x01);
62*4882a593Smuzhiyun 	smsc_config(IRQ_SELECT_INDEX, 8); /* IRQ8 */
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	/* XXX: PARPORT, KBD, and MOUSE will come here... */
65*4882a593Smuzhiyun 	outb_p(CONFIG_EXIT, CONFIG_PORT);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun static struct resource cf_ide_resources[] = {
70*4882a593Smuzhiyun 	[0] = {
71*4882a593Smuzhiyun 		.start  = PA_MRSHPC_IO + 0x1f0,
72*4882a593Smuzhiyun 		.end    = PA_MRSHPC_IO + 0x1f0 + 8,
73*4882a593Smuzhiyun 		.flags  = IORESOURCE_MEM,
74*4882a593Smuzhiyun 	},
75*4882a593Smuzhiyun 	[1] = {
76*4882a593Smuzhiyun 		.start  = PA_MRSHPC_IO + 0x1f0 + 0x206,
77*4882a593Smuzhiyun 		.end    = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8,
78*4882a593Smuzhiyun 		.flags  = IORESOURCE_MEM,
79*4882a593Smuzhiyun 	},
80*4882a593Smuzhiyun 	[2] = {
81*4882a593Smuzhiyun 		.start  = IRQ_CFCARD,
82*4882a593Smuzhiyun 		.flags  = IORESOURCE_IRQ,
83*4882a593Smuzhiyun 	},
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun static struct platform_device cf_ide_device  = {
87*4882a593Smuzhiyun 	.name           = "pata_platform",
88*4882a593Smuzhiyun 	.id             = -1,
89*4882a593Smuzhiyun 	.num_resources  = ARRAY_SIZE(cf_ide_resources),
90*4882a593Smuzhiyun 	.resource       = cf_ide_resources,
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun static struct heartbeat_data heartbeat_data = {
96*4882a593Smuzhiyun 	.bit_pos	= heartbeat_bit_pos,
97*4882a593Smuzhiyun 	.nr_bits	= ARRAY_SIZE(heartbeat_bit_pos),
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun static struct resource heartbeat_resource = {
101*4882a593Smuzhiyun 	.start	= PA_LED,
102*4882a593Smuzhiyun 	.end	= PA_LED,
103*4882a593Smuzhiyun 	.flags	= IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun static struct platform_device heartbeat_device = {
107*4882a593Smuzhiyun 	.name		= "heartbeat",
108*4882a593Smuzhiyun 	.id		= -1,
109*4882a593Smuzhiyun 	.dev	= {
110*4882a593Smuzhiyun 		.platform_data	= &heartbeat_data,
111*4882a593Smuzhiyun 	},
112*4882a593Smuzhiyun 	.num_resources	= 1,
113*4882a593Smuzhiyun 	.resource	= &heartbeat_resource,
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\
117*4882a593Smuzhiyun 	defined(CONFIG_CPU_SUBTYPE_SH7712)
118*4882a593Smuzhiyun /* SH771X Ethernet driver */
119*4882a593Smuzhiyun static struct sh_eth_plat_data sh_eth_plat = {
120*4882a593Smuzhiyun 	.phy = PHY_ID,
121*4882a593Smuzhiyun 	.phy_interface = PHY_INTERFACE_MODE_MII,
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun static struct resource sh_eth0_resources[] = {
125*4882a593Smuzhiyun 	[0] = {
126*4882a593Smuzhiyun 		.start = SH_ETH0_BASE,
127*4882a593Smuzhiyun 		.end = SH_ETH0_BASE + 0x1B8 - 1,
128*4882a593Smuzhiyun 		.flags = IORESOURCE_MEM,
129*4882a593Smuzhiyun 	},
130*4882a593Smuzhiyun 	[1] = {
131*4882a593Smuzhiyun 		.start = SH_TSU_BASE,
132*4882a593Smuzhiyun 		.end = SH_TSU_BASE + 0x200 - 1,
133*4882a593Smuzhiyun 		.flags = IORESOURCE_MEM,
134*4882a593Smuzhiyun 	},
135*4882a593Smuzhiyun 	[2] = {
136*4882a593Smuzhiyun 		.start = SH_ETH0_IRQ,
137*4882a593Smuzhiyun 		.end = SH_ETH0_IRQ,
138*4882a593Smuzhiyun 		.flags = IORESOURCE_IRQ,
139*4882a593Smuzhiyun 	},
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun static struct platform_device sh_eth0_device = {
143*4882a593Smuzhiyun 	.name = "sh771x-ether",
144*4882a593Smuzhiyun 	.id = 0,
145*4882a593Smuzhiyun 	.dev = {
146*4882a593Smuzhiyun 		.platform_data = &sh_eth_plat,
147*4882a593Smuzhiyun 	},
148*4882a593Smuzhiyun 	.num_resources = ARRAY_SIZE(sh_eth0_resources),
149*4882a593Smuzhiyun 	.resource = sh_eth0_resources,
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun static struct resource sh_eth1_resources[] = {
153*4882a593Smuzhiyun 	[0] = {
154*4882a593Smuzhiyun 		.start = SH_ETH1_BASE,
155*4882a593Smuzhiyun 		.end = SH_ETH1_BASE + 0x1B8 - 1,
156*4882a593Smuzhiyun 		.flags = IORESOURCE_MEM,
157*4882a593Smuzhiyun 	},
158*4882a593Smuzhiyun 	[1] = {
159*4882a593Smuzhiyun 		.start = SH_TSU_BASE,
160*4882a593Smuzhiyun 		.end = SH_TSU_BASE + 0x200 - 1,
161*4882a593Smuzhiyun 		.flags = IORESOURCE_MEM,
162*4882a593Smuzhiyun 	},
163*4882a593Smuzhiyun 	[2] = {
164*4882a593Smuzhiyun 		.start = SH_ETH1_IRQ,
165*4882a593Smuzhiyun 		.end = SH_ETH1_IRQ,
166*4882a593Smuzhiyun 		.flags = IORESOURCE_IRQ,
167*4882a593Smuzhiyun 	},
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun static struct platform_device sh_eth1_device = {
171*4882a593Smuzhiyun 	.name = "sh771x-ether",
172*4882a593Smuzhiyun 	.id = 1,
173*4882a593Smuzhiyun 	.dev = {
174*4882a593Smuzhiyun 		.platform_data = &sh_eth_plat,
175*4882a593Smuzhiyun 	},
176*4882a593Smuzhiyun 	.num_resources = ARRAY_SIZE(sh_eth1_resources),
177*4882a593Smuzhiyun 	.resource = sh_eth1_resources,
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun #endif
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun static struct platform_device *se_devices[] __initdata = {
182*4882a593Smuzhiyun 	&heartbeat_device,
183*4882a593Smuzhiyun 	&cf_ide_device,
184*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\
185*4882a593Smuzhiyun 	defined(CONFIG_CPU_SUBTYPE_SH7712)
186*4882a593Smuzhiyun 	&sh_eth0_device,
187*4882a593Smuzhiyun 	&sh_eth1_device,
188*4882a593Smuzhiyun #endif
189*4882a593Smuzhiyun };
190*4882a593Smuzhiyun 
se_devices_setup(void)191*4882a593Smuzhiyun static int __init se_devices_setup(void)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun 	mrshpc_setup_windows();
194*4882a593Smuzhiyun 	return platform_add_devices(se_devices, ARRAY_SIZE(se_devices));
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun device_initcall(se_devices_setup);
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun /*
199*4882a593Smuzhiyun  * The Machine Vector
200*4882a593Smuzhiyun  */
201*4882a593Smuzhiyun static struct sh_machine_vector mv_se __initmv = {
202*4882a593Smuzhiyun 	.mv_name		= "SolutionEngine",
203*4882a593Smuzhiyun 	.mv_setup		= smsc_setup,
204*4882a593Smuzhiyun 	.mv_init_irq		= init_se_IRQ,
205*4882a593Smuzhiyun };
206