1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/arch/sh/boards/se/770x/irq.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2000 Kazumoto Kojima
6*4882a593Smuzhiyun * Copyright (C) 2006 Nobuhiro Iwamatsu
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Hitachi SolutionEngine Support.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/irq.h>
15*4882a593Smuzhiyun #include <asm/irq.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include <mach-se/mach/se.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static struct ipr_data ipr_irq_table[] = {
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * Super I/O (Just mimic PC):
22*4882a593Smuzhiyun * 1: keyboard
23*4882a593Smuzhiyun * 3: serial 0
24*4882a593Smuzhiyun * 4: serial 1
25*4882a593Smuzhiyun * 5: printer
26*4882a593Smuzhiyun * 6: floppy
27*4882a593Smuzhiyun * 8: rtc
28*4882a593Smuzhiyun * 12: mouse
29*4882a593Smuzhiyun * 14: ide0
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7705)
32*4882a593Smuzhiyun /* This is default value */
33*4882a593Smuzhiyun { 13, 0, 8, 0x0f-13, },
34*4882a593Smuzhiyun { 5 , 0, 4, 0x0f- 5, },
35*4882a593Smuzhiyun { 10, 1, 0, 0x0f-10, },
36*4882a593Smuzhiyun { 7 , 2, 4, 0x0f- 7, },
37*4882a593Smuzhiyun { 3 , 2, 0, 0x0f- 3, },
38*4882a593Smuzhiyun { 1 , 3, 12, 0x0f- 1, },
39*4882a593Smuzhiyun { 12, 3, 4, 0x0f-12, }, /* LAN */
40*4882a593Smuzhiyun { 2 , 4, 8, 0x0f- 2, }, /* PCIRQ2 */
41*4882a593Smuzhiyun { 6 , 4, 4, 0x0f- 6, }, /* PCIRQ1 */
42*4882a593Smuzhiyun { 14, 4, 0, 0x0f-14, }, /* PCIRQ0 */
43*4882a593Smuzhiyun { 0 , 5, 12, 0x0f , },
44*4882a593Smuzhiyun { 4 , 5, 4, 0x0f- 4, },
45*4882a593Smuzhiyun { 8 , 6, 12, 0x0f- 8, },
46*4882a593Smuzhiyun { 9 , 6, 8, 0x0f- 9, },
47*4882a593Smuzhiyun { 11, 6, 4, 0x0f-11, },
48*4882a593Smuzhiyun #else
49*4882a593Smuzhiyun { 14, 0, 8, 0x0f-14, },
50*4882a593Smuzhiyun { 12, 0, 4, 0x0f-12, },
51*4882a593Smuzhiyun { 8, 1, 4, 0x0f- 8, },
52*4882a593Smuzhiyun { 6, 2, 12, 0x0f- 6, },
53*4882a593Smuzhiyun { 5, 2, 8, 0x0f- 5, },
54*4882a593Smuzhiyun { 4, 2, 4, 0x0f- 4, },
55*4882a593Smuzhiyun { 3, 2, 0, 0x0f- 3, },
56*4882a593Smuzhiyun { 1, 3, 12, 0x0f- 1, },
57*4882a593Smuzhiyun #if defined(CONFIG_STNIC)
58*4882a593Smuzhiyun /* ST NIC */
59*4882a593Smuzhiyun { 10, 3, 4, 0x0f-10, }, /* LAN */
60*4882a593Smuzhiyun #endif
61*4882a593Smuzhiyun /* MRSHPC IRQs setting */
62*4882a593Smuzhiyun { 0, 4, 12, 0x0f- 0, }, /* PCIRQ3 */
63*4882a593Smuzhiyun { 11, 4, 8, 0x0f-11, }, /* PCIRQ2 */
64*4882a593Smuzhiyun { 9, 4, 4, 0x0f- 9, }, /* PCIRQ1 */
65*4882a593Smuzhiyun { 7, 4, 0, 0x0f- 7, }, /* PCIRQ0 */
66*4882a593Smuzhiyun /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
67*4882a593Smuzhiyun /* NOTE: #2 and #13 are not used on PC */
68*4882a593Smuzhiyun { 13, 6, 4, 0x0f-13, }, /* SLOTIRQ2 */
69*4882a593Smuzhiyun { 2, 6, 0, 0x0f- 2, }, /* SLOTIRQ1 */
70*4882a593Smuzhiyun #endif
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static unsigned long ipr_offsets[] = {
74*4882a593Smuzhiyun BCR_ILCRA,
75*4882a593Smuzhiyun BCR_ILCRB,
76*4882a593Smuzhiyun BCR_ILCRC,
77*4882a593Smuzhiyun BCR_ILCRD,
78*4882a593Smuzhiyun BCR_ILCRE,
79*4882a593Smuzhiyun BCR_ILCRF,
80*4882a593Smuzhiyun BCR_ILCRG,
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static struct ipr_desc ipr_irq_desc = {
84*4882a593Smuzhiyun .ipr_offsets = ipr_offsets,
85*4882a593Smuzhiyun .nr_offsets = ARRAY_SIZE(ipr_offsets),
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun .ipr_data = ipr_irq_table,
88*4882a593Smuzhiyun .nr_irqs = ARRAY_SIZE(ipr_irq_table),
89*4882a593Smuzhiyun .chip = {
90*4882a593Smuzhiyun .name = "IPR-se770x",
91*4882a593Smuzhiyun },
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /*
95*4882a593Smuzhiyun * Initialize IRQ setting
96*4882a593Smuzhiyun */
init_se_IRQ(void)97*4882a593Smuzhiyun void __init init_se_IRQ(void)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun /* Disable all interrupts */
100*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRA);
101*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRB);
102*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRC);
103*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRD);
104*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRE);
105*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRF);
106*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRG);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun register_ipr_controller(&ipr_irq_desc);
109*4882a593Smuzhiyun }
110