1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * SDK7786 FPGA SRAM Support.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2010 Paul Mundt
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/string.h>
14*4882a593Smuzhiyun #include <mach/fpga.h>
15*4882a593Smuzhiyun #include <asm/sram.h>
16*4882a593Smuzhiyun #include <linux/sizes.h>
17*4882a593Smuzhiyun
fpga_sram_init(void)18*4882a593Smuzhiyun static int __init fpga_sram_init(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun unsigned long phys;
21*4882a593Smuzhiyun unsigned int area;
22*4882a593Smuzhiyun void __iomem *vaddr;
23*4882a593Smuzhiyun int ret;
24*4882a593Smuzhiyun u16 data;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Enable FPGA SRAM */
27*4882a593Smuzhiyun data = fpga_read_reg(LCLASR);
28*4882a593Smuzhiyun data |= LCLASR_FRAMEN;
29*4882a593Smuzhiyun fpga_write_reg(data, LCLASR);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * FPGA_SEL determines the area mapping
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun area = (data & LCLASR_FPGA_SEL_MASK) >> LCLASR_FPGA_SEL_SHIFT;
35*4882a593Smuzhiyun if (unlikely(area == LCLASR_AREA_MASK)) {
36*4882a593Smuzhiyun pr_err("FPGA memory unmapped.\n");
37*4882a593Smuzhiyun return -ENXIO;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /*
41*4882a593Smuzhiyun * The memory itself occupies a 2KiB range at the top of the area
42*4882a593Smuzhiyun * immediately below the system registers.
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun phys = (area << 26) + SZ_64M - SZ_4K;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /*
47*4882a593Smuzhiyun * The FPGA SRAM resides in translatable physical space, so set
48*4882a593Smuzhiyun * up a mapping prior to inserting it in to the pool.
49*4882a593Smuzhiyun */
50*4882a593Smuzhiyun vaddr = ioremap(phys, SZ_2K);
51*4882a593Smuzhiyun if (unlikely(!vaddr)) {
52*4882a593Smuzhiyun pr_err("Failed remapping FPGA memory.\n");
53*4882a593Smuzhiyun return -ENXIO;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun pr_info("Adding %dKiB of FPGA memory at 0x%08lx-0x%08lx "
57*4882a593Smuzhiyun "(area %d) to pool.\n",
58*4882a593Smuzhiyun SZ_2K >> 10, phys, phys + SZ_2K - 1, area);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun ret = gen_pool_add(sram_pool, (unsigned long)vaddr, SZ_2K, -1);
61*4882a593Smuzhiyun if (unlikely(ret < 0)) {
62*4882a593Smuzhiyun pr_err("Failed adding memory\n");
63*4882a593Smuzhiyun iounmap(vaddr);
64*4882a593Smuzhiyun return ret;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun postcore_initcall(fpga_sram_init);
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