1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Renesas Technology Europe SDK7786 Support.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2010 Matt Fleming
6*4882a593Smuzhiyun * Copyright (C) 2010 Paul Mundt
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/platform_device.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/regulator/fixed.h>
12*4882a593Smuzhiyun #include <linux/regulator/machine.h>
13*4882a593Smuzhiyun #include <linux/smsc911x.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/irq.h>
16*4882a593Smuzhiyun #include <linux/clk.h>
17*4882a593Smuzhiyun #include <linux/clkdev.h>
18*4882a593Smuzhiyun #include <mach/fpga.h>
19*4882a593Smuzhiyun #include <mach/irq.h>
20*4882a593Smuzhiyun #include <asm/machvec.h>
21*4882a593Smuzhiyun #include <asm/heartbeat.h>
22*4882a593Smuzhiyun #include <linux/sizes.h>
23*4882a593Smuzhiyun #include <asm/clock.h>
24*4882a593Smuzhiyun #include <asm/reboot.h>
25*4882a593Smuzhiyun #include <asm/smp-ops.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static struct resource heartbeat_resource = {
28*4882a593Smuzhiyun .start = 0x07fff8b0,
29*4882a593Smuzhiyun .end = 0x07fff8b0 + sizeof(u16) - 1,
30*4882a593Smuzhiyun .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static struct platform_device heartbeat_device = {
34*4882a593Smuzhiyun .name = "heartbeat",
35*4882a593Smuzhiyun .id = -1,
36*4882a593Smuzhiyun .num_resources = 1,
37*4882a593Smuzhiyun .resource = &heartbeat_resource,
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Dummy supplies, where voltage doesn't matter */
41*4882a593Smuzhiyun static struct regulator_consumer_supply dummy_supplies[] = {
42*4882a593Smuzhiyun REGULATOR_SUPPLY("vddvario", "smsc911x"),
43*4882a593Smuzhiyun REGULATOR_SUPPLY("vdd33a", "smsc911x"),
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun static struct resource smsc911x_resources[] = {
47*4882a593Smuzhiyun [0] = {
48*4882a593Smuzhiyun .name = "smsc911x-memory",
49*4882a593Smuzhiyun .start = 0x07ffff00,
50*4882a593Smuzhiyun .end = 0x07ffff00 + SZ_256 - 1,
51*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
52*4882a593Smuzhiyun },
53*4882a593Smuzhiyun [1] = {
54*4882a593Smuzhiyun .name = "smsc911x-irq",
55*4882a593Smuzhiyun .start = evt2irq(0x2c0),
56*4882a593Smuzhiyun .end = evt2irq(0x2c0),
57*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
58*4882a593Smuzhiyun },
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static struct smsc911x_platform_config smsc911x_config = {
62*4882a593Smuzhiyun .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
63*4882a593Smuzhiyun .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
64*4882a593Smuzhiyun .flags = SMSC911X_USE_32BIT,
65*4882a593Smuzhiyun .phy_interface = PHY_INTERFACE_MODE_MII,
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun static struct platform_device smsc911x_device = {
69*4882a593Smuzhiyun .name = "smsc911x",
70*4882a593Smuzhiyun .id = -1,
71*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(smsc911x_resources),
72*4882a593Smuzhiyun .resource = smsc911x_resources,
73*4882a593Smuzhiyun .dev = {
74*4882a593Smuzhiyun .platform_data = &smsc911x_config,
75*4882a593Smuzhiyun },
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun static struct resource smbus_fpga_resource = {
79*4882a593Smuzhiyun .start = 0x07fff9e0,
80*4882a593Smuzhiyun .end = 0x07fff9e0 + SZ_32 - 1,
81*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun static struct platform_device smbus_fpga_device = {
85*4882a593Smuzhiyun .name = "i2c-sdk7786",
86*4882a593Smuzhiyun .id = 0,
87*4882a593Smuzhiyun .num_resources = 1,
88*4882a593Smuzhiyun .resource = &smbus_fpga_resource,
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun static struct resource smbus_pcie_resource = {
92*4882a593Smuzhiyun .start = 0x07fffc30,
93*4882a593Smuzhiyun .end = 0x07fffc30 + SZ_32 - 1,
94*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun static struct platform_device smbus_pcie_device = {
98*4882a593Smuzhiyun .name = "i2c-sdk7786",
99*4882a593Smuzhiyun .id = 1,
100*4882a593Smuzhiyun .num_resources = 1,
101*4882a593Smuzhiyun .resource = &smbus_pcie_resource,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static struct i2c_board_info __initdata sdk7786_i2c_devices[] = {
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun I2C_BOARD_INFO("max6900", 0x68),
107*4882a593Smuzhiyun },
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun static struct platform_device *sh7786_devices[] __initdata = {
111*4882a593Smuzhiyun &heartbeat_device,
112*4882a593Smuzhiyun &smsc911x_device,
113*4882a593Smuzhiyun &smbus_fpga_device,
114*4882a593Smuzhiyun &smbus_pcie_device,
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun
sdk7786_i2c_setup(void)117*4882a593Smuzhiyun static int sdk7786_i2c_setup(void)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun unsigned int tmp;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /*
122*4882a593Smuzhiyun * Hand over I2C control to the FPGA.
123*4882a593Smuzhiyun */
124*4882a593Smuzhiyun tmp = fpga_read_reg(SBCR);
125*4882a593Smuzhiyun tmp &= ~SCBR_I2CCEN;
126*4882a593Smuzhiyun tmp |= SCBR_I2CMEN;
127*4882a593Smuzhiyun fpga_write_reg(tmp, SBCR);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun return i2c_register_board_info(0, sdk7786_i2c_devices,
130*4882a593Smuzhiyun ARRAY_SIZE(sdk7786_i2c_devices));
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
sdk7786_devices_setup(void)133*4882a593Smuzhiyun static int __init sdk7786_devices_setup(void)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun int ret;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun ret = platform_add_devices(sh7786_devices, ARRAY_SIZE(sh7786_devices));
138*4882a593Smuzhiyun if (unlikely(ret != 0))
139*4882a593Smuzhiyun return ret;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun return sdk7786_i2c_setup();
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun device_initcall(sdk7786_devices_setup);
144*4882a593Smuzhiyun
sdk7786_mode_pins(void)145*4882a593Smuzhiyun static int sdk7786_mode_pins(void)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun return fpga_read_reg(MODSWR);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /*
151*4882a593Smuzhiyun * FPGA-driven PCIe clocks
152*4882a593Smuzhiyun *
153*4882a593Smuzhiyun * Historically these include the oscillator, clock B (slots 2/3/4) and
154*4882a593Smuzhiyun * clock A (slot 1 and the CPU clock). Newer revs of the PCB shove
155*4882a593Smuzhiyun * everything under a single PCIe clocks enable bit that happens to map
156*4882a593Smuzhiyun * to the same bit position as the oscillator bit for earlier FPGA
157*4882a593Smuzhiyun * versions.
158*4882a593Smuzhiyun *
159*4882a593Smuzhiyun * Given that the legacy clocks have the side-effect of shutting the CPU
160*4882a593Smuzhiyun * off through the FPGA along with the PCI slots, we simply leave them in
161*4882a593Smuzhiyun * their initial state and don't bother registering them with the clock
162*4882a593Smuzhiyun * framework.
163*4882a593Smuzhiyun */
sdk7786_pcie_clk_enable(struct clk * clk)164*4882a593Smuzhiyun static int sdk7786_pcie_clk_enable(struct clk *clk)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR);
167*4882a593Smuzhiyun return 0;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
sdk7786_pcie_clk_disable(struct clk * clk)170*4882a593Smuzhiyun static void sdk7786_pcie_clk_disable(struct clk *clk)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun static struct sh_clk_ops sdk7786_pcie_clk_ops = {
176*4882a593Smuzhiyun .enable = sdk7786_pcie_clk_enable,
177*4882a593Smuzhiyun .disable = sdk7786_pcie_clk_disable,
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun static struct clk sdk7786_pcie_clk = {
181*4882a593Smuzhiyun .ops = &sdk7786_pcie_clk_ops,
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun static struct clk_lookup sdk7786_pcie_cl = {
185*4882a593Smuzhiyun .con_id = "pcie_plat_clk",
186*4882a593Smuzhiyun .clk = &sdk7786_pcie_clk,
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun
sdk7786_clk_init(void)189*4882a593Smuzhiyun static int sdk7786_clk_init(void)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun struct clk *clk;
192*4882a593Smuzhiyun int ret;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /*
195*4882a593Smuzhiyun * Only handle the EXTAL case, anyone interfacing a crystal
196*4882a593Smuzhiyun * resonator will need to provide their own input clock.
197*4882a593Smuzhiyun */
198*4882a593Smuzhiyun if (test_mode_pin(MODE_PIN9))
199*4882a593Smuzhiyun return -EINVAL;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun clk = clk_get(NULL, "extal");
202*4882a593Smuzhiyun if (IS_ERR(clk))
203*4882a593Smuzhiyun return PTR_ERR(clk);
204*4882a593Smuzhiyun ret = clk_set_rate(clk, 33333333);
205*4882a593Smuzhiyun clk_put(clk);
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /*
208*4882a593Smuzhiyun * Setup the FPGA clocks.
209*4882a593Smuzhiyun */
210*4882a593Smuzhiyun ret = clk_register(&sdk7786_pcie_clk);
211*4882a593Smuzhiyun if (unlikely(ret)) {
212*4882a593Smuzhiyun pr_err("FPGA clock registration failed\n");
213*4882a593Smuzhiyun return ret;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun clkdev_add(&sdk7786_pcie_cl);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun return 0;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
sdk7786_restart(char * cmd)221*4882a593Smuzhiyun static void sdk7786_restart(char *cmd)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun fpga_write_reg(0xa5a5, SRSTR);
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
sdk7786_power_off(void)226*4882a593Smuzhiyun static void sdk7786_power_off(void)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun fpga_write_reg(fpga_read_reg(PWRCR) | PWRCR_PDWNREQ, PWRCR);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun /*
231*4882a593Smuzhiyun * It can take up to 20us for the R8C to do its job, back off and
232*4882a593Smuzhiyun * wait a bit until we've been shut off. Even though newer FPGA
233*4882a593Smuzhiyun * versions don't set the ACK bit, the latency issue remains.
234*4882a593Smuzhiyun */
235*4882a593Smuzhiyun while ((fpga_read_reg(PWRCR) & PWRCR_PDWNACK) == 0)
236*4882a593Smuzhiyun cpu_sleep();
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun /* Initialize the board */
sdk7786_setup(char ** cmdline_p)240*4882a593Smuzhiyun static void __init sdk7786_setup(char **cmdline_p)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun pr_info("Renesas Technology Europe SDK7786 support:\n");
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun sdk7786_fpga_init();
247*4882a593Smuzhiyun sdk7786_nmi_init();
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun machine_ops.restart = sdk7786_restart;
252*4882a593Smuzhiyun pm_power_off = sdk7786_power_off;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun register_smp_ops(&shx3_smp_ops);
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun /*
258*4882a593Smuzhiyun * The Machine Vector
259*4882a593Smuzhiyun */
260*4882a593Smuzhiyun static struct sh_machine_vector mv_sdk7786 __initmv = {
261*4882a593Smuzhiyun .mv_name = "SDK7786",
262*4882a593Smuzhiyun .mv_setup = sdk7786_setup,
263*4882a593Smuzhiyun .mv_mode_pins = sdk7786_mode_pins,
264*4882a593Smuzhiyun .mv_clk_init = sdk7786_clk_init,
265*4882a593Smuzhiyun .mv_init_irq = sdk7786_init_irq,
266*4882a593Smuzhiyun };
267