1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * SDK7786 FPGA NMI Support.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2010 Paul Mundt
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/init.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/string.h>
10*4882a593Smuzhiyun #include <mach/fpga.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun enum {
13*4882a593Smuzhiyun NMI_MODE_MANUAL,
14*4882a593Smuzhiyun NMI_MODE_AUX,
15*4882a593Smuzhiyun NMI_MODE_MASKED,
16*4882a593Smuzhiyun NMI_MODE_ANY,
17*4882a593Smuzhiyun NMI_MODE_UNKNOWN,
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * Default to the manual NMI switch.
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun static unsigned int __initdata nmi_mode = NMI_MODE_ANY;
24*4882a593Smuzhiyun
nmi_mode_setup(char * str)25*4882a593Smuzhiyun static int __init nmi_mode_setup(char *str)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun if (!str)
28*4882a593Smuzhiyun return 0;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun if (strcmp(str, "manual") == 0)
31*4882a593Smuzhiyun nmi_mode = NMI_MODE_MANUAL;
32*4882a593Smuzhiyun else if (strcmp(str, "aux") == 0)
33*4882a593Smuzhiyun nmi_mode = NMI_MODE_AUX;
34*4882a593Smuzhiyun else if (strcmp(str, "masked") == 0)
35*4882a593Smuzhiyun nmi_mode = NMI_MODE_MASKED;
36*4882a593Smuzhiyun else if (strcmp(str, "any") == 0)
37*4882a593Smuzhiyun nmi_mode = NMI_MODE_ANY;
38*4882a593Smuzhiyun else {
39*4882a593Smuzhiyun nmi_mode = NMI_MODE_UNKNOWN;
40*4882a593Smuzhiyun pr_warn("Unknown NMI mode %s\n", str);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun printk("Set NMI mode to %d\n", nmi_mode);
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun early_param("nmi_mode", nmi_mode_setup);
47*4882a593Smuzhiyun
sdk7786_nmi_init(void)48*4882a593Smuzhiyun void __init sdk7786_nmi_init(void)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun unsigned int source, mask, tmp;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun switch (nmi_mode) {
53*4882a593Smuzhiyun case NMI_MODE_MANUAL:
54*4882a593Smuzhiyun source = NMISR_MAN_NMI;
55*4882a593Smuzhiyun mask = NMIMR_MAN_NMIM;
56*4882a593Smuzhiyun break;
57*4882a593Smuzhiyun case NMI_MODE_AUX:
58*4882a593Smuzhiyun source = NMISR_AUX_NMI;
59*4882a593Smuzhiyun mask = NMIMR_AUX_NMIM;
60*4882a593Smuzhiyun break;
61*4882a593Smuzhiyun case NMI_MODE_ANY:
62*4882a593Smuzhiyun source = NMISR_MAN_NMI | NMISR_AUX_NMI;
63*4882a593Smuzhiyun mask = NMIMR_MAN_NMIM | NMIMR_AUX_NMIM;
64*4882a593Smuzhiyun break;
65*4882a593Smuzhiyun case NMI_MODE_MASKED:
66*4882a593Smuzhiyun case NMI_MODE_UNKNOWN:
67*4882a593Smuzhiyun default:
68*4882a593Smuzhiyun source = mask = 0;
69*4882a593Smuzhiyun break;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Set the NMI source */
73*4882a593Smuzhiyun tmp = fpga_read_reg(NMISR);
74*4882a593Smuzhiyun tmp &= ~NMISR_MASK;
75*4882a593Smuzhiyun tmp |= source;
76*4882a593Smuzhiyun fpga_write_reg(tmp, NMISR);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* And the IRQ masking */
79*4882a593Smuzhiyun fpga_write_reg(NMIMR_MASK ^ mask, NMIMR);
80*4882a593Smuzhiyun }
81