1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * SDK7786 FPGA IRQ Controller Support.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2010 Matt Fleming
6*4882a593Smuzhiyun * Copyright (C) 2010 Paul Mundt
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/irq.h>
9*4882a593Smuzhiyun #include <mach/fpga.h>
10*4882a593Smuzhiyun #include <mach/irq.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun enum {
13*4882a593Smuzhiyun ATA_IRQ_BIT = 1,
14*4882a593Smuzhiyun SPI_BUSY_BIT = 2,
15*4882a593Smuzhiyun LIRQ5_BIT = 3,
16*4882a593Smuzhiyun LIRQ6_BIT = 4,
17*4882a593Smuzhiyun LIRQ7_BIT = 5,
18*4882a593Smuzhiyun LIRQ8_BIT = 6,
19*4882a593Smuzhiyun KEY_IRQ_BIT = 7,
20*4882a593Smuzhiyun PEN_IRQ_BIT = 8,
21*4882a593Smuzhiyun ETH_IRQ_BIT = 9,
22*4882a593Smuzhiyun RTC_ALARM_BIT = 10,
23*4882a593Smuzhiyun CRYSTAL_FAIL_BIT = 12,
24*4882a593Smuzhiyun ETH_PME_BIT = 14,
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
sdk7786_init_irq(void)27*4882a593Smuzhiyun void __init sdk7786_init_irq(void)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun unsigned int tmp;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Enable priority encoding for all IRLs */
32*4882a593Smuzhiyun fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Clear FPGA interrupt status registers */
35*4882a593Smuzhiyun fpga_write_reg(0x0000, INTASR);
36*4882a593Smuzhiyun fpga_write_reg(0x0000, INTBSR);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Unmask FPGA interrupts */
39*4882a593Smuzhiyun tmp = fpga_read_reg(INTAMR);
40*4882a593Smuzhiyun tmp &= ~(1 << ETH_IRQ_BIT);
41*4882a593Smuzhiyun fpga_write_reg(tmp, INTAMR);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun plat_irq_setup_pins(IRQ_MODE_IRL7654_MASK);
44*4882a593Smuzhiyun plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
45*4882a593Smuzhiyun }
46