1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * SDK7786 FPGA Support.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2010 Paul Mundt
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/init.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/bcd.h>
10*4882a593Smuzhiyun #include <mach/fpga.h>
11*4882a593Smuzhiyun #include <linux/sizes.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define FPGA_REGS_OFFSET 0x03fff800
14*4882a593Smuzhiyun #define FPGA_REGS_SIZE 0x490
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * The FPGA can be mapped in any of the generally available areas,
18*4882a593Smuzhiyun * so we attempt to scan for it using the fixed SRSTR read magic.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Once the FPGA is located, the rest of the mapping data for the other
21*4882a593Smuzhiyun * components can be determined dynamically from its section mapping
22*4882a593Smuzhiyun * registers.
23*4882a593Smuzhiyun */
sdk7786_fpga_probe(void)24*4882a593Smuzhiyun static void __iomem *sdk7786_fpga_probe(void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun unsigned long area;
27*4882a593Smuzhiyun void __iomem *base;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * Iterate over all of the areas where the FPGA could be mapped.
31*4882a593Smuzhiyun * The possible range is anywhere from area 0 through 6, area 7
32*4882a593Smuzhiyun * is reserved.
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun for (area = PA_AREA0; area < PA_AREA7; area += SZ_64M) {
35*4882a593Smuzhiyun base = ioremap(area + FPGA_REGS_OFFSET, FPGA_REGS_SIZE);
36*4882a593Smuzhiyun if (!base) {
37*4882a593Smuzhiyun /* Failed to remap this area, move along. */
38*4882a593Smuzhiyun continue;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun if (ioread16(base + SRSTR) == SRSTR_MAGIC)
42*4882a593Smuzhiyun return base; /* Found it! */
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun iounmap(base);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun return NULL;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun void __iomem *sdk7786_fpga_base;
51*4882a593Smuzhiyun
sdk7786_fpga_init(void)52*4882a593Smuzhiyun void __init sdk7786_fpga_init(void)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun u16 version, date;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun sdk7786_fpga_base = sdk7786_fpga_probe();
57*4882a593Smuzhiyun if (unlikely(!sdk7786_fpga_base)) {
58*4882a593Smuzhiyun panic("FPGA detection failed.\n");
59*4882a593Smuzhiyun return;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun version = fpga_read_reg(FPGAVR);
63*4882a593Smuzhiyun date = fpga_read_reg(FPGADR);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun pr_info("\tFPGA version:\t%d.%d (built on %d/%d/%d)\n",
66*4882a593Smuzhiyun bcd2bin(version >> 8) & 0xf, bcd2bin(version & 0xf),
67*4882a593Smuzhiyun ((date >> 12) & 0xf) + 2000,
68*4882a593Smuzhiyun (date >> 8) & 0xf, bcd2bin(date & 0xff));
69*4882a593Smuzhiyun }
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