xref: /OK3568_Linux_fs/kernel/arch/sh/boards/mach-r2d/setup.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Renesas Technology Sales RTS7751R2D Support.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2002 - 2006 Atom Create Engineering Co., Ltd.
6*4882a593Smuzhiyun  * Copyright (C) 2004 - 2007 Paul Mundt
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/platform_device.h>
10*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
11*4882a593Smuzhiyun #include <linux/mtd/partitions.h>
12*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
13*4882a593Smuzhiyun #include <linux/ata_platform.h>
14*4882a593Smuzhiyun #include <linux/sm501.h>
15*4882a593Smuzhiyun #include <linux/sm501-regs.h>
16*4882a593Smuzhiyun #include <linux/pm.h>
17*4882a593Smuzhiyun #include <linux/fb.h>
18*4882a593Smuzhiyun #include <linux/spi/spi.h>
19*4882a593Smuzhiyun #include <linux/spi/spi_bitbang.h>
20*4882a593Smuzhiyun #include <asm/machvec.h>
21*4882a593Smuzhiyun #include <mach/r2d.h>
22*4882a593Smuzhiyun #include <asm/io.h>
23*4882a593Smuzhiyun #include <asm/io_trapped.h>
24*4882a593Smuzhiyun #include <asm/spi.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun static struct resource cf_ide_resources[] = {
27*4882a593Smuzhiyun 	[0] = {
28*4882a593Smuzhiyun 		.start	= PA_AREA5_IO + 0x1000,
29*4882a593Smuzhiyun 		.end	= PA_AREA5_IO + 0x1000 + 0x10 - 0x2,
30*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
31*4882a593Smuzhiyun 	},
32*4882a593Smuzhiyun 	[1] = {
33*4882a593Smuzhiyun 		.start	= PA_AREA5_IO + 0x80c,
34*4882a593Smuzhiyun 		.end	= PA_AREA5_IO + 0x80c,
35*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
36*4882a593Smuzhiyun 	},
37*4882a593Smuzhiyun #ifndef CONFIG_RTS7751R2D_1 /* For R2D-1 polling is preferred */
38*4882a593Smuzhiyun 	[2] = {
39*4882a593Smuzhiyun 		.start	= IRQ_CF_IDE,
40*4882a593Smuzhiyun 		.flags	= IORESOURCE_IRQ,
41*4882a593Smuzhiyun 	},
42*4882a593Smuzhiyun #endif
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun static struct pata_platform_info pata_info = {
46*4882a593Smuzhiyun 	.ioport_shift	= 1,
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun static struct platform_device cf_ide_device  = {
50*4882a593Smuzhiyun 	.name		= "pata_platform",
51*4882a593Smuzhiyun 	.id		= -1,
52*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(cf_ide_resources),
53*4882a593Smuzhiyun 	.resource	= cf_ide_resources,
54*4882a593Smuzhiyun 	.dev	= {
55*4882a593Smuzhiyun 		.platform_data	= &pata_info,
56*4882a593Smuzhiyun 	},
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun static struct spi_board_info spi_bus[] = {
60*4882a593Smuzhiyun 	{
61*4882a593Smuzhiyun 		.modalias	= "rtc-r9701",
62*4882a593Smuzhiyun 		.max_speed_hz	= 1000000,
63*4882a593Smuzhiyun 		.mode		= SPI_MODE_3,
64*4882a593Smuzhiyun 	},
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
r2d_chip_select(struct sh_spi_info * spi,int cs,int state)67*4882a593Smuzhiyun static void r2d_chip_select(struct sh_spi_info *spi, int cs, int state)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	BUG_ON(cs != 0);  /* Single Epson RTC-9701JE attached on CS0 */
70*4882a593Smuzhiyun 	__raw_writew(state == BITBANG_CS_ACTIVE, PA_RTCCE);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun static struct sh_spi_info spi_info = {
74*4882a593Smuzhiyun 	.num_chipselect = 1,
75*4882a593Smuzhiyun 	.chip_select = r2d_chip_select,
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun static struct resource spi_sh_sci_resources[] = {
79*4882a593Smuzhiyun 	{
80*4882a593Smuzhiyun 		.start	= 0xffe00000,
81*4882a593Smuzhiyun 		.end	= 0xffe0001f,
82*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
83*4882a593Smuzhiyun 	},
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun static struct platform_device spi_sh_sci_device  = {
87*4882a593Smuzhiyun 	.name		= "spi_sh_sci",
88*4882a593Smuzhiyun 	.id		= -1,
89*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(spi_sh_sci_resources),
90*4882a593Smuzhiyun 	.resource	= spi_sh_sci_resources,
91*4882a593Smuzhiyun 	.dev	= {
92*4882a593Smuzhiyun 		.platform_data	= &spi_info,
93*4882a593Smuzhiyun 	},
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun static struct resource heartbeat_resources[] = {
97*4882a593Smuzhiyun 	[0] = {
98*4882a593Smuzhiyun 		.start	= PA_OUTPORT,
99*4882a593Smuzhiyun 		.end	= PA_OUTPORT,
100*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
101*4882a593Smuzhiyun 	},
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun static struct platform_device heartbeat_device = {
105*4882a593Smuzhiyun 	.name		= "heartbeat",
106*4882a593Smuzhiyun 	.id		= -1,
107*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(heartbeat_resources),
108*4882a593Smuzhiyun 	.resource	= heartbeat_resources,
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun static struct resource sm501_resources[] = {
112*4882a593Smuzhiyun 	[0]	= {
113*4882a593Smuzhiyun 		.start	= 0x10000000,
114*4882a593Smuzhiyun 		.end	= 0x13e00000 - 1,
115*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
116*4882a593Smuzhiyun 	},
117*4882a593Smuzhiyun 	[1]	= {
118*4882a593Smuzhiyun 		.start	= 0x13e00000,
119*4882a593Smuzhiyun 		.end	= 0x13ffffff,
120*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
121*4882a593Smuzhiyun 	},
122*4882a593Smuzhiyun 	[2]	= {
123*4882a593Smuzhiyun 		.start	= IRQ_VOYAGER,
124*4882a593Smuzhiyun 		.flags	= IORESOURCE_IRQ,
125*4882a593Smuzhiyun 	},
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun static struct fb_videomode sm501_default_mode = {
129*4882a593Smuzhiyun 	.pixclock	= 35714,
130*4882a593Smuzhiyun 	.xres		= 640,
131*4882a593Smuzhiyun 	.yres		= 480,
132*4882a593Smuzhiyun 	.left_margin	= 105,
133*4882a593Smuzhiyun 	.right_margin	= 50,
134*4882a593Smuzhiyun 	.upper_margin	= 35,
135*4882a593Smuzhiyun 	.lower_margin	= 0,
136*4882a593Smuzhiyun 	.hsync_len	= 96,
137*4882a593Smuzhiyun 	.vsync_len	= 2,
138*4882a593Smuzhiyun 	.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
142*4882a593Smuzhiyun 	.def_bpp	= 16,
143*4882a593Smuzhiyun 	.def_mode	= &sm501_default_mode,
144*4882a593Smuzhiyun 	.flags		= SM501FB_FLAG_USE_INIT_MODE |
145*4882a593Smuzhiyun 			  SM501FB_FLAG_USE_HWCURSOR |
146*4882a593Smuzhiyun 			  SM501FB_FLAG_USE_HWACCEL |
147*4882a593Smuzhiyun 			  SM501FB_FLAG_DISABLE_AT_EXIT,
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
151*4882a593Smuzhiyun 	.flags		= (SM501FB_FLAG_USE_INIT_MODE |
152*4882a593Smuzhiyun 			   SM501FB_FLAG_USE_HWCURSOR |
153*4882a593Smuzhiyun 			   SM501FB_FLAG_USE_HWACCEL |
154*4882a593Smuzhiyun 			   SM501FB_FLAG_DISABLE_AT_EXIT),
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun static struct sm501_platdata_fb sm501_fb_pdata = {
159*4882a593Smuzhiyun 	.fb_route	= SM501_FB_OWN,
160*4882a593Smuzhiyun 	.fb_crt		= &sm501_pdata_fbsub_crt,
161*4882a593Smuzhiyun 	.fb_pnl		= &sm501_pdata_fbsub_pnl,
162*4882a593Smuzhiyun 	.flags		= SM501_FBPD_SWAP_FB_ENDIAN,
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun static struct sm501_initdata sm501_initdata = {
166*4882a593Smuzhiyun 	.devices	= SM501_USE_USB_HOST | SM501_USE_UART0,
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun static struct sm501_platdata sm501_platform_data = {
170*4882a593Smuzhiyun 	.init		= &sm501_initdata,
171*4882a593Smuzhiyun 	.fb		= &sm501_fb_pdata,
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun static struct platform_device sm501_device = {
175*4882a593Smuzhiyun 	.name		= "sm501",
176*4882a593Smuzhiyun 	.id		= -1,
177*4882a593Smuzhiyun 	.dev		= {
178*4882a593Smuzhiyun 		.platform_data	= &sm501_platform_data,
179*4882a593Smuzhiyun 	},
180*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(sm501_resources),
181*4882a593Smuzhiyun 	.resource	= sm501_resources,
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun static struct mtd_partition r2d_partitions[] = {
185*4882a593Smuzhiyun 	{
186*4882a593Smuzhiyun 		.name		= "U-Boot",
187*4882a593Smuzhiyun 		.offset		= 0x00000000,
188*4882a593Smuzhiyun 		.size		= 0x00040000,
189*4882a593Smuzhiyun 		.mask_flags	= MTD_WRITEABLE,
190*4882a593Smuzhiyun 	}, {
191*4882a593Smuzhiyun 		.name		= "Environment",
192*4882a593Smuzhiyun 		.offset		= MTDPART_OFS_NXTBLK,
193*4882a593Smuzhiyun 		.size		= 0x00040000,
194*4882a593Smuzhiyun 		.mask_flags	= MTD_WRITEABLE,
195*4882a593Smuzhiyun 	}, {
196*4882a593Smuzhiyun 		.name		= "Kernel",
197*4882a593Smuzhiyun 		.offset		= MTDPART_OFS_NXTBLK,
198*4882a593Smuzhiyun 		.size		= 0x001c0000,
199*4882a593Smuzhiyun 	}, {
200*4882a593Smuzhiyun 		.name		= "Flash_FS",
201*4882a593Smuzhiyun 		.offset		= MTDPART_OFS_NXTBLK,
202*4882a593Smuzhiyun 		.size		= MTDPART_SIZ_FULL,
203*4882a593Smuzhiyun 	}
204*4882a593Smuzhiyun };
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun static struct physmap_flash_data flash_data = {
207*4882a593Smuzhiyun 	.width		= 2,
208*4882a593Smuzhiyun 	.nr_parts	= ARRAY_SIZE(r2d_partitions),
209*4882a593Smuzhiyun 	.parts		= r2d_partitions,
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun static struct resource flash_resource = {
213*4882a593Smuzhiyun 	.start		= 0x00000000,
214*4882a593Smuzhiyun 	.end		= 0x02000000,
215*4882a593Smuzhiyun 	.flags		= IORESOURCE_MEM,
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun static struct platform_device flash_device = {
219*4882a593Smuzhiyun 	.name		= "physmap-flash",
220*4882a593Smuzhiyun 	.id		= -1,
221*4882a593Smuzhiyun 	.resource	= &flash_resource,
222*4882a593Smuzhiyun 	.num_resources	= 1,
223*4882a593Smuzhiyun 	.dev		= {
224*4882a593Smuzhiyun 		.platform_data = &flash_data,
225*4882a593Smuzhiyun 	},
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun static struct platform_device *rts7751r2d_devices[] __initdata = {
229*4882a593Smuzhiyun 	&sm501_device,
230*4882a593Smuzhiyun 	&heartbeat_device,
231*4882a593Smuzhiyun 	&spi_sh_sci_device,
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun /*
235*4882a593Smuzhiyun  * The CF is connected with a 16-bit bus where 8-bit operations are
236*4882a593Smuzhiyun  * unsupported. The linux ata driver is however using 8-bit operations, so
237*4882a593Smuzhiyun  * insert a trapped io filter to convert 8-bit operations into 16-bit.
238*4882a593Smuzhiyun  */
239*4882a593Smuzhiyun static struct trapped_io cf_trapped_io = {
240*4882a593Smuzhiyun 	.resource		= cf_ide_resources,
241*4882a593Smuzhiyun 	.num_resources		= 2,
242*4882a593Smuzhiyun 	.minimum_bus_width	= 16,
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun 
rts7751r2d_devices_setup(void)245*4882a593Smuzhiyun static int __init rts7751r2d_devices_setup(void)
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun 	if (register_trapped_io(&cf_trapped_io) == 0)
248*4882a593Smuzhiyun 		platform_device_register(&cf_ide_device);
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	if (mach_is_r2d_plus())
251*4882a593Smuzhiyun 		platform_device_register(&flash_device);
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	return platform_add_devices(rts7751r2d_devices,
256*4882a593Smuzhiyun 				    ARRAY_SIZE(rts7751r2d_devices));
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun device_initcall(rts7751r2d_devices_setup);
259*4882a593Smuzhiyun 
rts7751r2d_power_off(void)260*4882a593Smuzhiyun static void rts7751r2d_power_off(void)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun 	__raw_writew(0x0001, PA_POWOFF);
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun /*
266*4882a593Smuzhiyun  * Initialize the board
267*4882a593Smuzhiyun  */
rts7751r2d_setup(char ** cmdline_p)268*4882a593Smuzhiyun static void __init rts7751r2d_setup(char **cmdline_p)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun 	void __iomem *sm501_reg;
271*4882a593Smuzhiyun 	u16 ver = __raw_readw(PA_VERREG);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	printk(KERN_INFO "Renesas Technology Sales RTS7751R2D support.\n");
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	printk(KERN_INFO "FPGA version:%d (revision:%d)\n",
276*4882a593Smuzhiyun 					(ver >> 4) & 0xf, ver & 0xf);
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	__raw_writew(0x0000, PA_OUTPORT);
279*4882a593Smuzhiyun 	pm_power_off = rts7751r2d_power_off;
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	/* sm501 dram configuration:
282*4882a593Smuzhiyun 	 * ColSizeX = 11 - External Memory Column Size: 256 words.
283*4882a593Smuzhiyun 	 * APX = 1 - External Memory Active to Pre-Charge Delay: 7 clocks.
284*4882a593Smuzhiyun 	 * RstX = 1 - External Memory Reset: Normal.
285*4882a593Smuzhiyun 	 * Rfsh = 1 - Local Memory Refresh to Command Delay: 12 clocks.
286*4882a593Smuzhiyun 	 * BwC =  1 - Local Memory Block Write Cycle Time: 2 clocks.
287*4882a593Smuzhiyun 	 * BwP =  1 - Local Memory Block Write to Pre-Charge Delay: 1 clock.
288*4882a593Smuzhiyun 	 * AP = 1 - Internal Memory Active to Pre-Charge Delay: 7 clocks.
289*4882a593Smuzhiyun 	 * Rst = 1 - Internal Memory Reset: Normal.
290*4882a593Smuzhiyun 	 * RA = 1 - Internal Memory Remain in Active State: Do not remain.
291*4882a593Smuzhiyun 	 */
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL;
294*4882a593Smuzhiyun 	writel(readl(sm501_reg) | 0x00f107c0, sm501_reg);
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun /*
298*4882a593Smuzhiyun  * The Machine Vector
299*4882a593Smuzhiyun  */
300*4882a593Smuzhiyun static struct sh_machine_vector mv_rts7751r2d __initmv = {
301*4882a593Smuzhiyun 	.mv_name		= "RTS7751R2D",
302*4882a593Smuzhiyun 	.mv_setup		= rts7751r2d_setup,
303*4882a593Smuzhiyun 	.mv_init_irq		= init_rts7751r2d_IRQ,
304*4882a593Smuzhiyun 	.mv_irq_demux		= rts7751r2d_irq_demux,
305*4882a593Smuzhiyun };
306