xref: /OK3568_Linux_fs/kernel/arch/sh/boards/mach-kfr2r09/setup.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * KFR2R09 board support code
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2009 Magnus Damm
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <asm/clock.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/machvec.h>
11*4882a593Smuzhiyun #include <asm/suspend.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <cpu/sh7724.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <linux/clkdev.h>
16*4882a593Smuzhiyun #include <linux/delay.h>
17*4882a593Smuzhiyun #include <linux/gpio.h>
18*4882a593Smuzhiyun #include <linux/gpio/machine.h>
19*4882a593Smuzhiyun #include <linux/i2c.h>
20*4882a593Smuzhiyun #include <linux/init.h>
21*4882a593Smuzhiyun #include <linux/input.h>
22*4882a593Smuzhiyun #include <linux/input/sh_keysc.h>
23*4882a593Smuzhiyun #include <linux/interrupt.h>
24*4882a593Smuzhiyun #include <linux/memblock.h>
25*4882a593Smuzhiyun #include <linux/mfd/tmio.h>
26*4882a593Smuzhiyun #include <linux/mmc/host.h>
27*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
28*4882a593Smuzhiyun #include <linux/platform_data/lv5207lp.h>
29*4882a593Smuzhiyun #include <linux/platform_device.h>
30*4882a593Smuzhiyun #include <linux/regulator/fixed.h>
31*4882a593Smuzhiyun #include <linux/regulator/machine.h>
32*4882a593Smuzhiyun #include <linux/sh_intc.h>
33*4882a593Smuzhiyun #include <linux/usb/r8a66597.h>
34*4882a593Smuzhiyun #include <linux/videodev2.h>
35*4882a593Smuzhiyun #include <linux/dma-map-ops.h>
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #include <mach/kfr2r09.h>
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #include <media/drv-intf/renesas-ceu.h>
40*4882a593Smuzhiyun #include <media/i2c/rj54n1cb0c.h>
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #include <video/sh_mobile_lcdc.h>
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define CEU_BUFFER_MEMORY_SIZE		(4 << 20)
45*4882a593Smuzhiyun static phys_addr_t ceu_dma_membase;
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /* set VIO_CKO clock to 25MHz */
48*4882a593Smuzhiyun #define CEU_MCLK_FREQ			25000000
49*4882a593Smuzhiyun #define DRVCRB				0xA405018C
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun static struct mtd_partition kfr2r09_nor_flash_partitions[] =
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun 	{
54*4882a593Smuzhiyun 		.name = "boot",
55*4882a593Smuzhiyun 		.offset = 0,
56*4882a593Smuzhiyun 		.size = (4 * 1024 * 1024),
57*4882a593Smuzhiyun 		.mask_flags = MTD_WRITEABLE,	/* Read-only */
58*4882a593Smuzhiyun 	},
59*4882a593Smuzhiyun 	{
60*4882a593Smuzhiyun 		.name = "other",
61*4882a593Smuzhiyun 		.offset = MTDPART_OFS_APPEND,
62*4882a593Smuzhiyun 		.size = MTDPART_SIZ_FULL,
63*4882a593Smuzhiyun 	},
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun static struct physmap_flash_data kfr2r09_nor_flash_data = {
67*4882a593Smuzhiyun 	.width		= 2,
68*4882a593Smuzhiyun 	.parts		= kfr2r09_nor_flash_partitions,
69*4882a593Smuzhiyun 	.nr_parts	= ARRAY_SIZE(kfr2r09_nor_flash_partitions),
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun static struct resource kfr2r09_nor_flash_resources[] = {
73*4882a593Smuzhiyun 	[0] = {
74*4882a593Smuzhiyun 		.name		= "NOR Flash",
75*4882a593Smuzhiyun 		.start		= 0x00000000,
76*4882a593Smuzhiyun 		.end		= 0x03ffffff,
77*4882a593Smuzhiyun 		.flags		= IORESOURCE_MEM,
78*4882a593Smuzhiyun 	}
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun static struct platform_device kfr2r09_nor_flash_device = {
82*4882a593Smuzhiyun 	.name		= "physmap-flash",
83*4882a593Smuzhiyun 	.resource	= kfr2r09_nor_flash_resources,
84*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(kfr2r09_nor_flash_resources),
85*4882a593Smuzhiyun 	.dev		= {
86*4882a593Smuzhiyun 		.platform_data = &kfr2r09_nor_flash_data,
87*4882a593Smuzhiyun 	},
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun static struct resource kfr2r09_nand_flash_resources[] = {
91*4882a593Smuzhiyun 	[0] = {
92*4882a593Smuzhiyun 		.name		= "NAND Flash",
93*4882a593Smuzhiyun 		.start		= 0x10000000,
94*4882a593Smuzhiyun 		.end		= 0x1001ffff,
95*4882a593Smuzhiyun 		.flags		= IORESOURCE_MEM,
96*4882a593Smuzhiyun 	}
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun static struct platform_device kfr2r09_nand_flash_device = {
100*4882a593Smuzhiyun 	.name		= "onenand-flash",
101*4882a593Smuzhiyun 	.resource	= kfr2r09_nand_flash_resources,
102*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(kfr2r09_nand_flash_resources),
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun static struct sh_keysc_info kfr2r09_sh_keysc_info = {
106*4882a593Smuzhiyun 	.mode = SH_KEYSC_MODE_1, /* KEYOUT0->4, KEYIN0->4 */
107*4882a593Smuzhiyun 	.scan_timing = 3,
108*4882a593Smuzhiyun 	.delay = 10,
109*4882a593Smuzhiyun 	.keycodes = {
110*4882a593Smuzhiyun 		KEY_PHONE, KEY_CLEAR, KEY_MAIL, KEY_WWW, KEY_ENTER,
111*4882a593Smuzhiyun 		KEY_1, KEY_2, KEY_3, 0, KEY_UP,
112*4882a593Smuzhiyun 		KEY_4, KEY_5, KEY_6, 0, KEY_LEFT,
113*4882a593Smuzhiyun 		KEY_7, KEY_8, KEY_9, KEY_PROG1, KEY_RIGHT,
114*4882a593Smuzhiyun 		KEY_S, KEY_0, KEY_P, KEY_PROG2, KEY_DOWN,
115*4882a593Smuzhiyun 		0, 0, 0, 0, 0
116*4882a593Smuzhiyun 	},
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun static struct resource kfr2r09_sh_keysc_resources[] = {
120*4882a593Smuzhiyun 	[0] = {
121*4882a593Smuzhiyun 		.name	= "KEYSC",
122*4882a593Smuzhiyun 		.start  = 0x044b0000,
123*4882a593Smuzhiyun 		.end    = 0x044b000f,
124*4882a593Smuzhiyun 		.flags  = IORESOURCE_MEM,
125*4882a593Smuzhiyun 	},
126*4882a593Smuzhiyun 	[1] = {
127*4882a593Smuzhiyun 		.start  = evt2irq(0xbe0),
128*4882a593Smuzhiyun 		.flags  = IORESOURCE_IRQ,
129*4882a593Smuzhiyun 	},
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun static struct platform_device kfr2r09_sh_keysc_device = {
133*4882a593Smuzhiyun 	.name           = "sh_keysc",
134*4882a593Smuzhiyun 	.id             = 0, /* "keysc0" clock */
135*4882a593Smuzhiyun 	.num_resources  = ARRAY_SIZE(kfr2r09_sh_keysc_resources),
136*4882a593Smuzhiyun 	.resource       = kfr2r09_sh_keysc_resources,
137*4882a593Smuzhiyun 	.dev	= {
138*4882a593Smuzhiyun 		.platform_data	= &kfr2r09_sh_keysc_info,
139*4882a593Smuzhiyun 	},
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun static const struct fb_videomode kfr2r09_lcdc_modes[] = {
143*4882a593Smuzhiyun 	{
144*4882a593Smuzhiyun 		.name = "TX07D34VM0AAA",
145*4882a593Smuzhiyun 		.xres = 240,
146*4882a593Smuzhiyun 		.yres = 400,
147*4882a593Smuzhiyun 		.left_margin = 0,
148*4882a593Smuzhiyun 		.right_margin = 16,
149*4882a593Smuzhiyun 		.hsync_len = 8,
150*4882a593Smuzhiyun 		.upper_margin = 0,
151*4882a593Smuzhiyun 		.lower_margin = 1,
152*4882a593Smuzhiyun 		.vsync_len = 1,
153*4882a593Smuzhiyun 		.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
154*4882a593Smuzhiyun 	},
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
158*4882a593Smuzhiyun 	.clock_source = LCDC_CLK_BUS,
159*4882a593Smuzhiyun 	.ch[0] = {
160*4882a593Smuzhiyun 		.chan = LCDC_CHAN_MAINLCD,
161*4882a593Smuzhiyun 		.fourcc = V4L2_PIX_FMT_RGB565,
162*4882a593Smuzhiyun 		.interface_type = SYS18,
163*4882a593Smuzhiyun 		.clock_divider = 6,
164*4882a593Smuzhiyun 		.flags = LCDC_FLAGS_DWPOL,
165*4882a593Smuzhiyun 		.lcd_modes = kfr2r09_lcdc_modes,
166*4882a593Smuzhiyun 		.num_modes = ARRAY_SIZE(kfr2r09_lcdc_modes),
167*4882a593Smuzhiyun 		.panel_cfg = {
168*4882a593Smuzhiyun 			.width = 35,
169*4882a593Smuzhiyun 			.height = 58,
170*4882a593Smuzhiyun 			.setup_sys = kfr2r09_lcd_setup,
171*4882a593Smuzhiyun 			.start_transfer = kfr2r09_lcd_start,
172*4882a593Smuzhiyun 		},
173*4882a593Smuzhiyun 		.sys_bus_cfg = {
174*4882a593Smuzhiyun 			.ldmt2r = 0x07010904,
175*4882a593Smuzhiyun 			.ldmt3r = 0x14012914,
176*4882a593Smuzhiyun 			/* set 1s delay to encourage fsync() */
177*4882a593Smuzhiyun 			.deferred_io_msec = 1000,
178*4882a593Smuzhiyun 		},
179*4882a593Smuzhiyun 	}
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun static struct resource kfr2r09_sh_lcdc_resources[] = {
183*4882a593Smuzhiyun 	[0] = {
184*4882a593Smuzhiyun 		.name	= "LCDC",
185*4882a593Smuzhiyun 		.start	= 0xfe940000, /* P4-only space */
186*4882a593Smuzhiyun 		.end	= 0xfe942fff,
187*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
188*4882a593Smuzhiyun 	},
189*4882a593Smuzhiyun 	[1] = {
190*4882a593Smuzhiyun 		.start	= evt2irq(0xf40),
191*4882a593Smuzhiyun 		.flags	= IORESOURCE_IRQ,
192*4882a593Smuzhiyun 	},
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun static struct platform_device kfr2r09_sh_lcdc_device = {
196*4882a593Smuzhiyun 	.name		= "sh_mobile_lcdc_fb",
197*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(kfr2r09_sh_lcdc_resources),
198*4882a593Smuzhiyun 	.resource	= kfr2r09_sh_lcdc_resources,
199*4882a593Smuzhiyun 	.dev	= {
200*4882a593Smuzhiyun 		.platform_data	= &kfr2r09_sh_lcdc_info,
201*4882a593Smuzhiyun 	},
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun static struct lv5207lp_platform_data kfr2r09_backlight_data = {
205*4882a593Smuzhiyun 	.fbdev = &kfr2r09_sh_lcdc_device.dev,
206*4882a593Smuzhiyun 	.def_value = 13,
207*4882a593Smuzhiyun 	.max_value = 13,
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun static struct i2c_board_info kfr2r09_backlight_board_info = {
211*4882a593Smuzhiyun 	I2C_BOARD_INFO("lv5207lp", 0x75),
212*4882a593Smuzhiyun 	.platform_data = &kfr2r09_backlight_data,
213*4882a593Smuzhiyun };
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun static struct r8a66597_platdata kfr2r09_usb0_gadget_data = {
216*4882a593Smuzhiyun 	.on_chip = 1,
217*4882a593Smuzhiyun };
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun static struct resource kfr2r09_usb0_gadget_resources[] = {
220*4882a593Smuzhiyun 	[0] = {
221*4882a593Smuzhiyun 		.start	= 0x04d80000,
222*4882a593Smuzhiyun 		.end	= 0x04d80123,
223*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
224*4882a593Smuzhiyun 	},
225*4882a593Smuzhiyun 	[1] = {
226*4882a593Smuzhiyun 		.start	= evt2irq(0xa20),
227*4882a593Smuzhiyun 		.end	= evt2irq(0xa20),
228*4882a593Smuzhiyun 		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
229*4882a593Smuzhiyun 	},
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun static struct platform_device kfr2r09_usb0_gadget_device = {
233*4882a593Smuzhiyun 	.name		= "r8a66597_udc",
234*4882a593Smuzhiyun 	.id		= 0,
235*4882a593Smuzhiyun 	.dev = {
236*4882a593Smuzhiyun 		.dma_mask		= NULL,         /*  not use dma */
237*4882a593Smuzhiyun 		.coherent_dma_mask	= 0xffffffff,
238*4882a593Smuzhiyun 		.platform_data	= &kfr2r09_usb0_gadget_data,
239*4882a593Smuzhiyun 	},
240*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(kfr2r09_usb0_gadget_resources),
241*4882a593Smuzhiyun 	.resource	= kfr2r09_usb0_gadget_resources,
242*4882a593Smuzhiyun };
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun static struct ceu_platform_data ceu_pdata = {
245*4882a593Smuzhiyun 	.num_subdevs			= 1,
246*4882a593Smuzhiyun 	.subdevs = {
247*4882a593Smuzhiyun 		{ /* [0] = rj54n1cb0c */
248*4882a593Smuzhiyun 			.flags		= 0,
249*4882a593Smuzhiyun 			.bus_width	= 8,
250*4882a593Smuzhiyun 			.bus_shift	= 0,
251*4882a593Smuzhiyun 			.i2c_adapter_id	= 1,
252*4882a593Smuzhiyun 			.i2c_address	= 0x50,
253*4882a593Smuzhiyun 		},
254*4882a593Smuzhiyun 	},
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun static struct resource kfr2r09_ceu_resources[] = {
258*4882a593Smuzhiyun 	[0] = {
259*4882a593Smuzhiyun 		.name	= "CEU",
260*4882a593Smuzhiyun 		.start	= 0xfe910000,
261*4882a593Smuzhiyun 		.end	= 0xfe91009f,
262*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
263*4882a593Smuzhiyun 	},
264*4882a593Smuzhiyun 	[1] = {
265*4882a593Smuzhiyun 		.start  = evt2irq(0x880),
266*4882a593Smuzhiyun 		.end	= evt2irq(0x880),
267*4882a593Smuzhiyun 		.flags  = IORESOURCE_IRQ,
268*4882a593Smuzhiyun 	},
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun static struct platform_device kfr2r09_ceu_device = {
272*4882a593Smuzhiyun 	.name		= "renesas-ceu",
273*4882a593Smuzhiyun 	.id             = 0, /* "ceu0" clock */
274*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(kfr2r09_ceu_resources),
275*4882a593Smuzhiyun 	.resource	= kfr2r09_ceu_resources,
276*4882a593Smuzhiyun 	.dev	= {
277*4882a593Smuzhiyun 		.platform_data	= &ceu_pdata,
278*4882a593Smuzhiyun 	},
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun static struct rj54n1_pdata rj54n1_priv = {
282*4882a593Smuzhiyun 	.mclk_freq	= CEU_MCLK_FREQ,
283*4882a593Smuzhiyun 	.ioctl_high	= false,
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun static struct i2c_board_info kfr2r09_i2c_camera = {
287*4882a593Smuzhiyun 	I2C_BOARD_INFO("rj54n1cb0c", 0x50),
288*4882a593Smuzhiyun 	.platform_data = &rj54n1_priv,
289*4882a593Smuzhiyun };
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun static struct gpiod_lookup_table rj54n1_gpios = {
292*4882a593Smuzhiyun 	.dev_id		= "1-0050",
293*4882a593Smuzhiyun 	.table		= {
294*4882a593Smuzhiyun 		GPIO_LOOKUP("sh7724_pfc", GPIO_PTB4, "poweron",
295*4882a593Smuzhiyun 			    GPIO_ACTIVE_HIGH),
296*4882a593Smuzhiyun 		GPIO_LOOKUP("sh7724_pfc", GPIO_PTB7, "enable",
297*4882a593Smuzhiyun 			    GPIO_ACTIVE_HIGH),
298*4882a593Smuzhiyun 	},
299*4882a593Smuzhiyun };
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun /* Fixed 3.3V regulator to be used by SDHI0 */
302*4882a593Smuzhiyun static struct regulator_consumer_supply fixed3v3_power_consumers[] =
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun 	REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
305*4882a593Smuzhiyun 	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
306*4882a593Smuzhiyun };
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun static struct resource kfr2r09_sh_sdhi0_resources[] = {
309*4882a593Smuzhiyun 	[0] = {
310*4882a593Smuzhiyun 		.name	= "SDHI0",
311*4882a593Smuzhiyun 		.start  = 0x04ce0000,
312*4882a593Smuzhiyun 		.end    = 0x04ce00ff,
313*4882a593Smuzhiyun 		.flags  = IORESOURCE_MEM,
314*4882a593Smuzhiyun 	},
315*4882a593Smuzhiyun 	[1] = {
316*4882a593Smuzhiyun 		.start  = evt2irq(0xe80),
317*4882a593Smuzhiyun 		.flags  = IORESOURCE_IRQ,
318*4882a593Smuzhiyun 	},
319*4882a593Smuzhiyun };
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun static struct tmio_mmc_data sh7724_sdhi0_data = {
322*4882a593Smuzhiyun 	.chan_priv_tx	= (void *)SHDMA_SLAVE_SDHI0_TX,
323*4882a593Smuzhiyun 	.chan_priv_rx	= (void *)SHDMA_SLAVE_SDHI0_RX,
324*4882a593Smuzhiyun 	.capabilities	= MMC_CAP_SDIO_IRQ,
325*4882a593Smuzhiyun 	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
326*4882a593Smuzhiyun };
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun static struct platform_device kfr2r09_sh_sdhi0_device = {
329*4882a593Smuzhiyun 	.name           = "sh_mobile_sdhi",
330*4882a593Smuzhiyun 	.num_resources  = ARRAY_SIZE(kfr2r09_sh_sdhi0_resources),
331*4882a593Smuzhiyun 	.resource       = kfr2r09_sh_sdhi0_resources,
332*4882a593Smuzhiyun 	.dev = {
333*4882a593Smuzhiyun 		.platform_data	= &sh7724_sdhi0_data,
334*4882a593Smuzhiyun 	},
335*4882a593Smuzhiyun };
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun static struct platform_device *kfr2r09_devices[] __initdata = {
338*4882a593Smuzhiyun 	&kfr2r09_nor_flash_device,
339*4882a593Smuzhiyun 	&kfr2r09_nand_flash_device,
340*4882a593Smuzhiyun 	&kfr2r09_sh_keysc_device,
341*4882a593Smuzhiyun 	&kfr2r09_sh_lcdc_device,
342*4882a593Smuzhiyun 	&kfr2r09_sh_sdhi0_device,
343*4882a593Smuzhiyun };
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun #define BSC_CS0BCR 0xfec10004
346*4882a593Smuzhiyun #define BSC_CS0WCR 0xfec10024
347*4882a593Smuzhiyun #define BSC_CS4BCR 0xfec10010
348*4882a593Smuzhiyun #define BSC_CS4WCR 0xfec10030
349*4882a593Smuzhiyun #define PORT_MSELCRB 0xa4050182
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun #ifdef CONFIG_I2C
kfr2r09_usb0_gadget_i2c_setup(void)352*4882a593Smuzhiyun static int kfr2r09_usb0_gadget_i2c_setup(void)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun 	struct i2c_adapter *a;
355*4882a593Smuzhiyun 	struct i2c_msg msg;
356*4882a593Smuzhiyun 	unsigned char buf[2];
357*4882a593Smuzhiyun 	int ret;
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	a = i2c_get_adapter(0);
360*4882a593Smuzhiyun 	if (!a)
361*4882a593Smuzhiyun 		return -ENODEV;
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	/* set bit 1 (the second bit) of chip at 0x09, register 0x13 */
364*4882a593Smuzhiyun 	buf[0] = 0x13;
365*4882a593Smuzhiyun 	msg.addr = 0x09;
366*4882a593Smuzhiyun 	msg.buf = buf;
367*4882a593Smuzhiyun 	msg.len = 1;
368*4882a593Smuzhiyun 	msg.flags = 0;
369*4882a593Smuzhiyun 	ret = i2c_transfer(a, &msg, 1);
370*4882a593Smuzhiyun 	if (ret != 1)
371*4882a593Smuzhiyun 		return -ENODEV;
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	buf[0] = 0;
374*4882a593Smuzhiyun 	msg.addr = 0x09;
375*4882a593Smuzhiyun 	msg.buf = buf;
376*4882a593Smuzhiyun 	msg.len = 1;
377*4882a593Smuzhiyun 	msg.flags = I2C_M_RD;
378*4882a593Smuzhiyun 	ret = i2c_transfer(a, &msg, 1);
379*4882a593Smuzhiyun 	if (ret != 1)
380*4882a593Smuzhiyun 		return -ENODEV;
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	buf[1] = buf[0] | (1 << 1);
383*4882a593Smuzhiyun 	buf[0] = 0x13;
384*4882a593Smuzhiyun 	msg.addr = 0x09;
385*4882a593Smuzhiyun 	msg.buf = buf;
386*4882a593Smuzhiyun 	msg.len = 2;
387*4882a593Smuzhiyun 	msg.flags = 0;
388*4882a593Smuzhiyun 	ret = i2c_transfer(a, &msg, 1);
389*4882a593Smuzhiyun 	if (ret != 1)
390*4882a593Smuzhiyun 		return -ENODEV;
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	return 0;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun 
kfr2r09_serial_i2c_setup(void)395*4882a593Smuzhiyun static int kfr2r09_serial_i2c_setup(void)
396*4882a593Smuzhiyun {
397*4882a593Smuzhiyun 	struct i2c_adapter *a;
398*4882a593Smuzhiyun 	struct i2c_msg msg;
399*4882a593Smuzhiyun 	unsigned char buf[2];
400*4882a593Smuzhiyun 	int ret;
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun 	a = i2c_get_adapter(0);
403*4882a593Smuzhiyun 	if (!a)
404*4882a593Smuzhiyun 		return -ENODEV;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	/* set bit 6 (the 7th bit) of chip at 0x09, register 0x13 */
407*4882a593Smuzhiyun 	buf[0] = 0x13;
408*4882a593Smuzhiyun 	msg.addr = 0x09;
409*4882a593Smuzhiyun 	msg.buf = buf;
410*4882a593Smuzhiyun 	msg.len = 1;
411*4882a593Smuzhiyun 	msg.flags = 0;
412*4882a593Smuzhiyun 	ret = i2c_transfer(a, &msg, 1);
413*4882a593Smuzhiyun 	if (ret != 1)
414*4882a593Smuzhiyun 		return -ENODEV;
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	buf[0] = 0;
417*4882a593Smuzhiyun 	msg.addr = 0x09;
418*4882a593Smuzhiyun 	msg.buf = buf;
419*4882a593Smuzhiyun 	msg.len = 1;
420*4882a593Smuzhiyun 	msg.flags = I2C_M_RD;
421*4882a593Smuzhiyun 	ret = i2c_transfer(a, &msg, 1);
422*4882a593Smuzhiyun 	if (ret != 1)
423*4882a593Smuzhiyun 		return -ENODEV;
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	buf[1] = buf[0] | (1 << 6);
426*4882a593Smuzhiyun 	buf[0] = 0x13;
427*4882a593Smuzhiyun 	msg.addr = 0x09;
428*4882a593Smuzhiyun 	msg.buf = buf;
429*4882a593Smuzhiyun 	msg.len = 2;
430*4882a593Smuzhiyun 	msg.flags = 0;
431*4882a593Smuzhiyun 	ret = i2c_transfer(a, &msg, 1);
432*4882a593Smuzhiyun 	if (ret != 1)
433*4882a593Smuzhiyun 		return -ENODEV;
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	return 0;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun #else
kfr2r09_usb0_gadget_i2c_setup(void)438*4882a593Smuzhiyun static int kfr2r09_usb0_gadget_i2c_setup(void)
439*4882a593Smuzhiyun {
440*4882a593Smuzhiyun 	return -ENODEV;
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun 
kfr2r09_serial_i2c_setup(void)443*4882a593Smuzhiyun static int kfr2r09_serial_i2c_setup(void)
444*4882a593Smuzhiyun {
445*4882a593Smuzhiyun 	return -ENODEV;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun #endif
448*4882a593Smuzhiyun 
kfr2r09_usb0_gadget_setup(void)449*4882a593Smuzhiyun static int kfr2r09_usb0_gadget_setup(void)
450*4882a593Smuzhiyun {
451*4882a593Smuzhiyun 	int plugged_in;
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 	gpio_request(GPIO_PTN4, NULL); /* USB_DET */
454*4882a593Smuzhiyun 	gpio_direction_input(GPIO_PTN4);
455*4882a593Smuzhiyun 	plugged_in = gpio_get_value(GPIO_PTN4);
456*4882a593Smuzhiyun 	if (!plugged_in)
457*4882a593Smuzhiyun 		return -ENODEV; /* no cable plugged in */
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	if (kfr2r09_usb0_gadget_i2c_setup() != 0)
460*4882a593Smuzhiyun 		return -ENODEV; /* unable to configure using i2c */
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	__raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
463*4882a593Smuzhiyun 	gpio_request(GPIO_FN_PDSTATUS, NULL); /* R-standby disables USB clock */
464*4882a593Smuzhiyun 	gpio_request(GPIO_PTV6, NULL); /* USBCLK_ON */
465*4882a593Smuzhiyun 	gpio_direction_output(GPIO_PTV6, 1); /* USBCLK_ON = H */
466*4882a593Smuzhiyun 	msleep(20); /* wait 20ms to let the clock settle */
467*4882a593Smuzhiyun 	clk_enable(clk_get(NULL, "usb0"));
468*4882a593Smuzhiyun 	__raw_writew(0x0600, 0xa40501d4);
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	return 0;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun extern char kfr2r09_sdram_enter_start;
474*4882a593Smuzhiyun extern char kfr2r09_sdram_enter_end;
475*4882a593Smuzhiyun extern char kfr2r09_sdram_leave_start;
476*4882a593Smuzhiyun extern char kfr2r09_sdram_leave_end;
477*4882a593Smuzhiyun 
kfr2r09_devices_setup(void)478*4882a593Smuzhiyun static int __init kfr2r09_devices_setup(void)
479*4882a593Smuzhiyun {
480*4882a593Smuzhiyun 	struct clk *camera_clk;
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	/* register board specific self-refresh code */
483*4882a593Smuzhiyun 	sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
484*4882a593Smuzhiyun 					SUSP_SH_RSTANDBY,
485*4882a593Smuzhiyun 					&kfr2r09_sdram_enter_start,
486*4882a593Smuzhiyun 					&kfr2r09_sdram_enter_end,
487*4882a593Smuzhiyun 					&kfr2r09_sdram_leave_start,
488*4882a593Smuzhiyun 					&kfr2r09_sdram_leave_end);
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
491*4882a593Smuzhiyun 				     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun 	/* enable SCIF1 serial port for YC401 console support */
494*4882a593Smuzhiyun 	gpio_request(GPIO_FN_SCIF1_RXD, NULL);
495*4882a593Smuzhiyun 	gpio_request(GPIO_FN_SCIF1_TXD, NULL);
496*4882a593Smuzhiyun 	kfr2r09_serial_i2c_setup(); /* ECONTMSK(bit6=L10ONEN) set 1 */
497*4882a593Smuzhiyun 	gpio_request(GPIO_PTG3, NULL); /* HPON_ON */
498*4882a593Smuzhiyun 	gpio_direction_output(GPIO_PTG3, 1); /* HPON_ON = H */
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 	/* setup NOR flash at CS0 */
501*4882a593Smuzhiyun 	__raw_writel(0x36db0400, BSC_CS0BCR);
502*4882a593Smuzhiyun 	__raw_writel(0x00000500, BSC_CS0WCR);
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	/* setup NAND flash at CS4 */
505*4882a593Smuzhiyun 	__raw_writel(0x36db0400, BSC_CS4BCR);
506*4882a593Smuzhiyun 	__raw_writel(0x00000500, BSC_CS4WCR);
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	/* setup KEYSC pins */
509*4882a593Smuzhiyun 	gpio_request(GPIO_FN_KEYOUT0, NULL);
510*4882a593Smuzhiyun 	gpio_request(GPIO_FN_KEYOUT1, NULL);
511*4882a593Smuzhiyun 	gpio_request(GPIO_FN_KEYOUT2, NULL);
512*4882a593Smuzhiyun 	gpio_request(GPIO_FN_KEYOUT3, NULL);
513*4882a593Smuzhiyun 	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
514*4882a593Smuzhiyun 	gpio_request(GPIO_FN_KEYIN0, NULL);
515*4882a593Smuzhiyun 	gpio_request(GPIO_FN_KEYIN1, NULL);
516*4882a593Smuzhiyun 	gpio_request(GPIO_FN_KEYIN2, NULL);
517*4882a593Smuzhiyun 	gpio_request(GPIO_FN_KEYIN3, NULL);
518*4882a593Smuzhiyun 	gpio_request(GPIO_FN_KEYIN4, NULL);
519*4882a593Smuzhiyun 	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun 	/* setup LCDC pins for SYS panel */
522*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD17, NULL);
523*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD16, NULL);
524*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD15, NULL);
525*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD14, NULL);
526*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD13, NULL);
527*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD12, NULL);
528*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD11, NULL);
529*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD10, NULL);
530*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD9, NULL);
531*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD8, NULL);
532*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD7, NULL);
533*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD6, NULL);
534*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD5, NULL);
535*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD4, NULL);
536*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD3, NULL);
537*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD2, NULL);
538*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD1, NULL);
539*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDD0, NULL);
540*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDRS, NULL); /* LCD_RS */
541*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDCS, NULL); /* LCD_CS/ */
542*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDRD, NULL); /* LCD_RD/ */
543*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDWR, NULL); /* LCD_WR/ */
544*4882a593Smuzhiyun 	gpio_request(GPIO_FN_LCDVSYN, NULL); /* LCD_VSYNC */
545*4882a593Smuzhiyun 	gpio_request(GPIO_PTE4, NULL); /* LCD_RST/ */
546*4882a593Smuzhiyun 	gpio_direction_output(GPIO_PTE4, 1);
547*4882a593Smuzhiyun 	gpio_request(GPIO_PTF4, NULL); /* PROTECT/ */
548*4882a593Smuzhiyun 	gpio_direction_output(GPIO_PTF4, 1);
549*4882a593Smuzhiyun 	gpio_request(GPIO_PTU0, NULL); /* LEDSTDBY/ */
550*4882a593Smuzhiyun 	gpio_direction_output(GPIO_PTU0, 1);
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 	/* setup USB function */
553*4882a593Smuzhiyun 	if (kfr2r09_usb0_gadget_setup() == 0)
554*4882a593Smuzhiyun 		platform_device_register(&kfr2r09_usb0_gadget_device);
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	/* CEU */
557*4882a593Smuzhiyun 	gpio_request(GPIO_FN_VIO_CKO, NULL);
558*4882a593Smuzhiyun 	gpio_request(GPIO_FN_VIO0_CLK, NULL);
559*4882a593Smuzhiyun 	gpio_request(GPIO_FN_VIO0_VD, NULL);
560*4882a593Smuzhiyun 	gpio_request(GPIO_FN_VIO0_HD, NULL);
561*4882a593Smuzhiyun 	gpio_request(GPIO_FN_VIO0_FLD, NULL);
562*4882a593Smuzhiyun 	gpio_request(GPIO_FN_VIO0_D7, NULL);
563*4882a593Smuzhiyun 	gpio_request(GPIO_FN_VIO0_D6, NULL);
564*4882a593Smuzhiyun 	gpio_request(GPIO_FN_VIO0_D5, NULL);
565*4882a593Smuzhiyun 	gpio_request(GPIO_FN_VIO0_D4, NULL);
566*4882a593Smuzhiyun 	gpio_request(GPIO_FN_VIO0_D3, NULL);
567*4882a593Smuzhiyun 	gpio_request(GPIO_FN_VIO0_D2, NULL);
568*4882a593Smuzhiyun 	gpio_request(GPIO_FN_VIO0_D1, NULL);
569*4882a593Smuzhiyun 	gpio_request(GPIO_FN_VIO0_D0, NULL);
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	/* SDHI0 connected to yc304 */
572*4882a593Smuzhiyun 	gpio_request(GPIO_FN_SDHI0CD, NULL);
573*4882a593Smuzhiyun 	gpio_request(GPIO_FN_SDHI0D3, NULL);
574*4882a593Smuzhiyun 	gpio_request(GPIO_FN_SDHI0D2, NULL);
575*4882a593Smuzhiyun 	gpio_request(GPIO_FN_SDHI0D1, NULL);
576*4882a593Smuzhiyun 	gpio_request(GPIO_FN_SDHI0D0, NULL);
577*4882a593Smuzhiyun 	gpio_request(GPIO_FN_SDHI0CMD, NULL);
578*4882a593Smuzhiyun 	gpio_request(GPIO_FN_SDHI0CLK, NULL);
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	i2c_register_board_info(0, &kfr2r09_backlight_board_info, 1);
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 	/* Set camera clock frequency and register and alias for rj54n1. */
583*4882a593Smuzhiyun 	camera_clk = clk_get(NULL, "video_clk");
584*4882a593Smuzhiyun 	if (!IS_ERR(camera_clk)) {
585*4882a593Smuzhiyun 		clk_set_rate(camera_clk,
586*4882a593Smuzhiyun 			     clk_round_rate(camera_clk, CEU_MCLK_FREQ));
587*4882a593Smuzhiyun 		clk_put(camera_clk);
588*4882a593Smuzhiyun 	}
589*4882a593Smuzhiyun 	clk_add_alias(NULL, "1-0050", "video_clk", NULL);
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	/* set DRVCRB
592*4882a593Smuzhiyun 	 *
593*4882a593Smuzhiyun 	 * use 1.8 V for VccQ_VIO
594*4882a593Smuzhiyun 	 * use 2.85V for VccQ_SR
595*4882a593Smuzhiyun 	 */
596*4882a593Smuzhiyun 	__raw_writew((__raw_readw(DRVCRB) & ~0x0003) | 0x0001, DRVCRB);
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun 	gpiod_add_lookup_table(&rj54n1_gpios);
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun 	i2c_register_board_info(1, &kfr2r09_i2c_camera, 1);
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun 	/* Initialize CEU platform device separately to map memory first */
603*4882a593Smuzhiyun 	device_initialize(&kfr2r09_ceu_device.dev);
604*4882a593Smuzhiyun 	dma_declare_coherent_memory(&kfr2r09_ceu_device.dev,
605*4882a593Smuzhiyun 			ceu_dma_membase, ceu_dma_membase,
606*4882a593Smuzhiyun 			ceu_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1);
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun 	platform_device_add(&kfr2r09_ceu_device);
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 	return platform_add_devices(kfr2r09_devices,
611*4882a593Smuzhiyun 				    ARRAY_SIZE(kfr2r09_devices));
612*4882a593Smuzhiyun }
613*4882a593Smuzhiyun device_initcall(kfr2r09_devices_setup);
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun /* Return the board specific boot mode pin configuration */
kfr2r09_mode_pins(void)616*4882a593Smuzhiyun static int kfr2r09_mode_pins(void)
617*4882a593Smuzhiyun {
618*4882a593Smuzhiyun 	/* MD0=1, MD1=1, MD2=0: Clock Mode 3
619*4882a593Smuzhiyun 	 * MD3=0: 16-bit Area0 Bus Width
620*4882a593Smuzhiyun 	 * MD5=1: Little Endian
621*4882a593Smuzhiyun 	 * MD8=1: Test Mode Disabled
622*4882a593Smuzhiyun 	 */
623*4882a593Smuzhiyun 	return MODE_PIN0 | MODE_PIN1 | MODE_PIN5 | MODE_PIN8;
624*4882a593Smuzhiyun }
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun /* Reserve a portion of memory for CEU buffers */
kfr2r09_mv_mem_reserve(void)627*4882a593Smuzhiyun static void __init kfr2r09_mv_mem_reserve(void)
628*4882a593Smuzhiyun {
629*4882a593Smuzhiyun 	phys_addr_t phys;
630*4882a593Smuzhiyun 	phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun 	phys = memblock_phys_alloc(size, PAGE_SIZE);
633*4882a593Smuzhiyun 	if (!phys)
634*4882a593Smuzhiyun 		panic("Failed to allocate CEU memory\n");
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun 	memblock_free(phys, size);
637*4882a593Smuzhiyun 	memblock_remove(phys, size);
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun 	ceu_dma_membase = phys;
640*4882a593Smuzhiyun }
641*4882a593Smuzhiyun 
642*4882a593Smuzhiyun /*
643*4882a593Smuzhiyun  * The Machine Vector
644*4882a593Smuzhiyun  */
645*4882a593Smuzhiyun static struct sh_machine_vector mv_kfr2r09 __initmv = {
646*4882a593Smuzhiyun 	.mv_name		= "kfr2r09",
647*4882a593Smuzhiyun 	.mv_mode_pins		= kfr2r09_mode_pins,
648*4882a593Smuzhiyun 	.mv_mem_reserve         = kfr2r09_mv_mem_reserve,
649*4882a593Smuzhiyun };
650