1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * hp6x0 Power Management Routines
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2006 Andriy Skulysh <askulsyh@gmail.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/init.h>
8*4882a593Smuzhiyun #include <linux/suspend.h>
9*4882a593Smuzhiyun #include <linux/errno.h>
10*4882a593Smuzhiyun #include <linux/time.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/gfp.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun #include <asm/hd64461.h>
15*4882a593Smuzhiyun #include <asm/bl_bit.h>
16*4882a593Smuzhiyun #include <mach/hp6xx.h>
17*4882a593Smuzhiyun #include <cpu/dac.h>
18*4882a593Smuzhiyun #include <asm/freq.h>
19*4882a593Smuzhiyun #include <asm/watchdog.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define INTR_OFFSET 0x600
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define STBCR 0xffffff82
24*4882a593Smuzhiyun #define STBCR2 0xffffff88
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define STBCR_STBY 0x80
27*4882a593Smuzhiyun #define STBCR_MSTP2 0x04
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define MCR 0xffffff68
30*4882a593Smuzhiyun #define RTCNT 0xffffff70
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define MCR_RMODE 2
33*4882a593Smuzhiyun #define MCR_RFSH 4
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun extern u8 wakeup_start;
36*4882a593Smuzhiyun extern u8 wakeup_end;
37*4882a593Smuzhiyun
pm_enter(void)38*4882a593Smuzhiyun static void pm_enter(void)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun u8 stbcr, csr;
41*4882a593Smuzhiyun u16 frqcr, mcr;
42*4882a593Smuzhiyun u32 vbr_new, vbr_old;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun set_bl_bit();
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* set wdt */
47*4882a593Smuzhiyun csr = sh_wdt_read_csr();
48*4882a593Smuzhiyun csr &= ~WTCSR_TME;
49*4882a593Smuzhiyun csr |= WTCSR_CKS_4096;
50*4882a593Smuzhiyun sh_wdt_write_csr(csr);
51*4882a593Smuzhiyun csr = sh_wdt_read_csr();
52*4882a593Smuzhiyun sh_wdt_write_cnt(0);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* disable PLL1 */
55*4882a593Smuzhiyun frqcr = __raw_readw(FRQCR);
56*4882a593Smuzhiyun frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY);
57*4882a593Smuzhiyun __raw_writew(frqcr, FRQCR);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* enable standby */
60*4882a593Smuzhiyun stbcr = __raw_readb(STBCR);
61*4882a593Smuzhiyun __raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* set self-refresh */
64*4882a593Smuzhiyun mcr = __raw_readw(MCR);
65*4882a593Smuzhiyun __raw_writew(mcr & ~MCR_RFSH, MCR);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* set interrupt handler */
68*4882a593Smuzhiyun asm volatile("stc vbr, %0" : "=r" (vbr_old));
69*4882a593Smuzhiyun vbr_new = get_zeroed_page(GFP_ATOMIC);
70*4882a593Smuzhiyun udelay(50);
71*4882a593Smuzhiyun memcpy((void*)(vbr_new + INTR_OFFSET),
72*4882a593Smuzhiyun &wakeup_start, &wakeup_end - &wakeup_start);
73*4882a593Smuzhiyun asm volatile("ldc %0, vbr" : : "r" (vbr_new));
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun __raw_writew(0, RTCNT);
76*4882a593Smuzhiyun __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun cpu_sleep();
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun asm volatile("ldc %0, vbr" : : "r" (vbr_old));
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun free_page(vbr_new);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* enable PLL1 */
85*4882a593Smuzhiyun frqcr = __raw_readw(FRQCR);
86*4882a593Smuzhiyun frqcr |= FRQCR_PSTBY;
87*4882a593Smuzhiyun __raw_writew(frqcr, FRQCR);
88*4882a593Smuzhiyun udelay(50);
89*4882a593Smuzhiyun frqcr |= FRQCR_PLLEN;
90*4882a593Smuzhiyun __raw_writew(frqcr, FRQCR);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun __raw_writeb(stbcr, STBCR);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun clear_bl_bit();
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
hp6x0_pm_enter(suspend_state_t state)97*4882a593Smuzhiyun static int hp6x0_pm_enter(suspend_state_t state)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun u8 stbcr, stbcr2;
100*4882a593Smuzhiyun #ifdef CONFIG_HD64461_ENABLER
101*4882a593Smuzhiyun u8 scr;
102*4882a593Smuzhiyun u16 hd64461_stbcr;
103*4882a593Smuzhiyun #endif
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #ifdef CONFIG_HD64461_ENABLER
106*4882a593Smuzhiyun outb(0, HD64461_PCC1CSCIER);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun scr = inb(HD64461_PCC1SCR);
109*4882a593Smuzhiyun scr |= HD64461_PCCSCR_VCC1;
110*4882a593Smuzhiyun outb(scr, HD64461_PCC1SCR);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun hd64461_stbcr = inw(HD64461_STBCR);
113*4882a593Smuzhiyun hd64461_stbcr |= HD64461_STBCR_SPC1ST;
114*4882a593Smuzhiyun outw(hd64461_stbcr, HD64461_STBCR);
115*4882a593Smuzhiyun #endif
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun __raw_writeb(0x1f, DACR);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun stbcr = __raw_readb(STBCR);
120*4882a593Smuzhiyun __raw_writeb(0x01, STBCR);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun stbcr2 = __raw_readb(STBCR2);
123*4882a593Smuzhiyun __raw_writeb(0x7f , STBCR2);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun outw(0xf07f, HD64461_SCPUCR);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun pm_enter();
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun outw(0, HD64461_SCPUCR);
130*4882a593Smuzhiyun __raw_writeb(stbcr, STBCR);
131*4882a593Smuzhiyun __raw_writeb(stbcr2, STBCR2);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun #ifdef CONFIG_HD64461_ENABLER
134*4882a593Smuzhiyun hd64461_stbcr = inw(HD64461_STBCR);
135*4882a593Smuzhiyun hd64461_stbcr &= ~HD64461_STBCR_SPC1ST;
136*4882a593Smuzhiyun outw(hd64461_stbcr, HD64461_STBCR);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun outb(0x4c, HD64461_PCC1CSCIER);
139*4882a593Smuzhiyun outb(0x00, HD64461_PCC1CSCR);
140*4882a593Smuzhiyun #endif
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun return 0;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static const struct platform_suspend_ops hp6x0_pm_ops = {
146*4882a593Smuzhiyun .enter = hp6x0_pm_enter,
147*4882a593Smuzhiyun .valid = suspend_valid_only_mem,
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun
hp6x0_pm_init(void)150*4882a593Smuzhiyun static int __init hp6x0_pm_init(void)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun suspend_set_ops(&hp6x0_pm_ops);
153*4882a593Smuzhiyun return 0;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun late_initcall(hp6x0_pm_init);
157