1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Renesas Solutions Highlander R7785RP Support.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2002 Atom Create Engineering Co., Ltd.
6*4882a593Smuzhiyun * Copyright (C) 2006 - 2008 Paul Mundt
7*4882a593Smuzhiyun * Copyright (C) 2007 Magnus Damm
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/irq.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <mach/highlander.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun enum {
15*4882a593Smuzhiyun UNUSED = 0,
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* FPGA specific interrupt sources */
18*4882a593Smuzhiyun CF, /* Compact Flash */
19*4882a593Smuzhiyun SMBUS, /* SMBUS */
20*4882a593Smuzhiyun TP, /* Touch panel */
21*4882a593Smuzhiyun RTC, /* RTC Alarm */
22*4882a593Smuzhiyun TH_ALERT, /* Temperature sensor */
23*4882a593Smuzhiyun AX88796, /* Ethernet controller */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* external bus connector */
26*4882a593Smuzhiyun EXT0, EXT1, EXT2, EXT3, EXT4, EXT5, EXT6, EXT7,
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static struct intc_vect vectors[] __initdata = {
30*4882a593Smuzhiyun INTC_IRQ(CF, IRQ_CF),
31*4882a593Smuzhiyun INTC_IRQ(SMBUS, IRQ_SMBUS),
32*4882a593Smuzhiyun INTC_IRQ(TP, IRQ_TP),
33*4882a593Smuzhiyun INTC_IRQ(RTC, IRQ_RTC),
34*4882a593Smuzhiyun INTC_IRQ(TH_ALERT, IRQ_TH_ALERT),
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun INTC_IRQ(EXT0, IRQ_EXT0), INTC_IRQ(EXT1, IRQ_EXT1),
37*4882a593Smuzhiyun INTC_IRQ(EXT2, IRQ_EXT2), INTC_IRQ(EXT3, IRQ_EXT3),
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun INTC_IRQ(EXT4, IRQ_EXT4), INTC_IRQ(EXT5, IRQ_EXT5),
40*4882a593Smuzhiyun INTC_IRQ(EXT6, IRQ_EXT6), INTC_IRQ(EXT7, IRQ_EXT7),
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun INTC_IRQ(AX88796, IRQ_AX88796),
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static struct intc_mask_reg mask_registers[] __initdata = {
46*4882a593Smuzhiyun { 0xa4000010, 0, 16, /* IRLMCR1 */
47*4882a593Smuzhiyun { 0, 0, 0, 0, CF, AX88796, SMBUS, TP,
48*4882a593Smuzhiyun RTC, 0, TH_ALERT, 0, 0, 0, 0, 0 } },
49*4882a593Smuzhiyun { 0xa4000012, 0, 16, /* IRLMCR2 */
50*4882a593Smuzhiyun { 0, 0, 0, 0, 0, 0, 0, 0,
51*4882a593Smuzhiyun EXT7, EXT6, EXT5, EXT4, EXT3, EXT2, EXT1, EXT0 } },
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static unsigned char irl2irq[HL_NR_IRL] __initdata = {
55*4882a593Smuzhiyun 0, IRQ_CF, IRQ_EXT4, IRQ_EXT5,
56*4882a593Smuzhiyun IRQ_EXT6, IRQ_EXT7, IRQ_SMBUS, IRQ_TP,
57*4882a593Smuzhiyun IRQ_RTC, IRQ_TH_ALERT, IRQ_AX88796, IRQ_EXT0,
58*4882a593Smuzhiyun IRQ_EXT1, IRQ_EXT2, IRQ_EXT3,
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
62*4882a593Smuzhiyun NULL, mask_registers, NULL, NULL);
63*4882a593Smuzhiyun
highlander_plat_irq_setup(void)64*4882a593Smuzhiyun unsigned char * __init highlander_plat_irq_setup(void)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun if ((__raw_readw(0xa4000158) & 0xf000) != 0x1000)
67*4882a593Smuzhiyun return NULL;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun printk(KERN_INFO "Using r7785rp interrupt controller.\n");
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun __raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* Setup the FPGA IRL */
74*4882a593Smuzhiyun __raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */
75*4882a593Smuzhiyun __raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */
76*4882a593Smuzhiyun __raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */
77*4882a593Smuzhiyun __raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */
78*4882a593Smuzhiyun __raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */
79*4882a593Smuzhiyun __raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun register_intc_controller(&intc_desc);
82*4882a593Smuzhiyun return irl2irq;
83*4882a593Smuzhiyun }
84