1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2009 Renesas Solutions Corp.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <asm/clock.h>
8*4882a593Smuzhiyun #include <asm/heartbeat.h>
9*4882a593Smuzhiyun #include <asm/suspend.h>
10*4882a593Smuzhiyun #include <cpu/sh7724.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/input.h>
17*4882a593Smuzhiyun #include <linux/input/sh_keysc.h>
18*4882a593Smuzhiyun #include <linux/interrupt.h>
19*4882a593Smuzhiyun #include <linux/memblock.h>
20*4882a593Smuzhiyun #include <linux/mfd/tmio.h>
21*4882a593Smuzhiyun #include <linux/mmc/host.h>
22*4882a593Smuzhiyun #include <linux/mmc/sh_mmcif.h>
23*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
24*4882a593Smuzhiyun #include <linux/gpio.h>
25*4882a593Smuzhiyun #include <linux/gpio/machine.h>
26*4882a593Smuzhiyun #include <linux/platform_data/gpio_backlight.h>
27*4882a593Smuzhiyun #include <linux/platform_data/tsc2007.h>
28*4882a593Smuzhiyun #include <linux/platform_device.h>
29*4882a593Smuzhiyun #include <linux/regulator/fixed.h>
30*4882a593Smuzhiyun #include <linux/regulator/machine.h>
31*4882a593Smuzhiyun #include <linux/sh_eth.h>
32*4882a593Smuzhiyun #include <linux/sh_intc.h>
33*4882a593Smuzhiyun #include <linux/spi/mmc_spi.h>
34*4882a593Smuzhiyun #include <linux/spi/sh_msiof.h>
35*4882a593Smuzhiyun #include <linux/spi/spi.h>
36*4882a593Smuzhiyun #include <linux/usb/r8a66597.h>
37*4882a593Smuzhiyun #include <linux/usb/renesas_usbhs.h>
38*4882a593Smuzhiyun #include <linux/videodev2.h>
39*4882a593Smuzhiyun #include <linux/dma-map-ops.h>
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #include <media/drv-intf/renesas-ceu.h>
42*4882a593Smuzhiyun #include <media/i2c/mt9t112.h>
43*4882a593Smuzhiyun #include <media/i2c/tw9910.h>
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #include <sound/sh_fsi.h>
46*4882a593Smuzhiyun #include <sound/simple_card.h>
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #include <video/sh_mobile_lcdc.h>
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /*
51*4882a593Smuzhiyun * Address Interface BusWidth
52*4882a593Smuzhiyun *-----------------------------------------
53*4882a593Smuzhiyun * 0x0000_0000 uboot 16bit
54*4882a593Smuzhiyun * 0x0004_0000 Linux romImage 16bit
55*4882a593Smuzhiyun * 0x0014_0000 MTD for Linux 16bit
56*4882a593Smuzhiyun * 0x0400_0000 Internal I/O 16/32bit
57*4882a593Smuzhiyun * 0x0800_0000 DRAM 32bit
58*4882a593Smuzhiyun * 0x1800_0000 MFI 16bit
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* SWITCH
62*4882a593Smuzhiyun *------------------------------
63*4882a593Smuzhiyun * DS2[1] = FlashROM write protect ON : write protect
64*4882a593Smuzhiyun * OFF : No write protect
65*4882a593Smuzhiyun * DS2[2] = RMII / TS, SCIF ON : RMII
66*4882a593Smuzhiyun * OFF : TS, SCIF3
67*4882a593Smuzhiyun * DS2[3] = Camera / Video ON : Camera
68*4882a593Smuzhiyun * OFF : NTSC/PAL (IN)
69*4882a593Smuzhiyun * DS2[5] = NTSC_OUT Clock ON : On board OSC
70*4882a593Smuzhiyun * OFF : SH7724 DV_CLK
71*4882a593Smuzhiyun * DS2[6-7] = MMC / SD ON-OFF : SD
72*4882a593Smuzhiyun * OFF-ON : MMC
73*4882a593Smuzhiyun */
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /*
76*4882a593Smuzhiyun * FSI - DA7210
77*4882a593Smuzhiyun *
78*4882a593Smuzhiyun * it needs amixer settings for playing
79*4882a593Smuzhiyun *
80*4882a593Smuzhiyun * amixer set 'HeadPhone' 80
81*4882a593Smuzhiyun * amixer set 'Out Mixer Left DAC Left' on
82*4882a593Smuzhiyun * amixer set 'Out Mixer Right DAC Right' on
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define CEU_BUFFER_MEMORY_SIZE (4 << 20)
86*4882a593Smuzhiyun static phys_addr_t ceu0_dma_membase;
87*4882a593Smuzhiyun static phys_addr_t ceu1_dma_membase;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Heartbeat */
90*4882a593Smuzhiyun static unsigned char led_pos[] = { 0, 1, 2, 3 };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun static struct heartbeat_data heartbeat_data = {
93*4882a593Smuzhiyun .nr_bits = 4,
94*4882a593Smuzhiyun .bit_pos = led_pos,
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun static struct resource heartbeat_resource = {
98*4882a593Smuzhiyun .start = 0xA405012C, /* PTG */
99*4882a593Smuzhiyun .end = 0xA405012E - 1,
100*4882a593Smuzhiyun .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static struct platform_device heartbeat_device = {
104*4882a593Smuzhiyun .name = "heartbeat",
105*4882a593Smuzhiyun .id = -1,
106*4882a593Smuzhiyun .dev = {
107*4882a593Smuzhiyun .platform_data = &heartbeat_data,
108*4882a593Smuzhiyun },
109*4882a593Smuzhiyun .num_resources = 1,
110*4882a593Smuzhiyun .resource = &heartbeat_resource,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* MTD */
114*4882a593Smuzhiyun static struct mtd_partition nor_flash_partitions[] = {
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun .name = "boot loader",
117*4882a593Smuzhiyun .offset = 0,
118*4882a593Smuzhiyun .size = (5 * 1024 * 1024),
119*4882a593Smuzhiyun .mask_flags = MTD_WRITEABLE, /* force read-only */
120*4882a593Smuzhiyun }, {
121*4882a593Smuzhiyun .name = "free-area",
122*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
123*4882a593Smuzhiyun .size = MTDPART_SIZ_FULL,
124*4882a593Smuzhiyun },
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun static struct physmap_flash_data nor_flash_data = {
128*4882a593Smuzhiyun .width = 2,
129*4882a593Smuzhiyun .parts = nor_flash_partitions,
130*4882a593Smuzhiyun .nr_parts = ARRAY_SIZE(nor_flash_partitions),
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun static struct resource nor_flash_resources[] = {
134*4882a593Smuzhiyun [0] = {
135*4882a593Smuzhiyun .name = "NOR Flash",
136*4882a593Smuzhiyun .start = 0x00000000,
137*4882a593Smuzhiyun .end = 0x03ffffff,
138*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun static struct platform_device nor_flash_device = {
143*4882a593Smuzhiyun .name = "physmap-flash",
144*4882a593Smuzhiyun .resource = nor_flash_resources,
145*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(nor_flash_resources),
146*4882a593Smuzhiyun .dev = {
147*4882a593Smuzhiyun .platform_data = &nor_flash_data,
148*4882a593Smuzhiyun },
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun /* SH Eth */
152*4882a593Smuzhiyun #define SH_ETH_ADDR (0xA4600000)
153*4882a593Smuzhiyun static struct resource sh_eth_resources[] = {
154*4882a593Smuzhiyun [0] = {
155*4882a593Smuzhiyun .start = SH_ETH_ADDR,
156*4882a593Smuzhiyun .end = SH_ETH_ADDR + 0x1FC,
157*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
158*4882a593Smuzhiyun },
159*4882a593Smuzhiyun [1] = {
160*4882a593Smuzhiyun .start = evt2irq(0xd60),
161*4882a593Smuzhiyun .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
162*4882a593Smuzhiyun },
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun static struct sh_eth_plat_data sh_eth_plat = {
166*4882a593Smuzhiyun .phy = 0x1f, /* SMSC LAN8700 */
167*4882a593Smuzhiyun .phy_interface = PHY_INTERFACE_MODE_MII,
168*4882a593Smuzhiyun .ether_link_active_low = 1
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun static struct platform_device sh_eth_device = {
172*4882a593Smuzhiyun .name = "sh7724-ether",
173*4882a593Smuzhiyun .id = 0,
174*4882a593Smuzhiyun .dev = {
175*4882a593Smuzhiyun .platform_data = &sh_eth_plat,
176*4882a593Smuzhiyun },
177*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(sh_eth_resources),
178*4882a593Smuzhiyun .resource = sh_eth_resources,
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun /* USB0 host */
usb0_port_power(int port,int power)182*4882a593Smuzhiyun static void usb0_port_power(int port, int power)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun gpio_set_value(GPIO_PTB4, power);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun static struct r8a66597_platdata usb0_host_data = {
188*4882a593Smuzhiyun .on_chip = 1,
189*4882a593Smuzhiyun .port_power = usb0_port_power,
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun static struct resource usb0_host_resources[] = {
193*4882a593Smuzhiyun [0] = {
194*4882a593Smuzhiyun .start = 0xa4d80000,
195*4882a593Smuzhiyun .end = 0xa4d80124 - 1,
196*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
197*4882a593Smuzhiyun },
198*4882a593Smuzhiyun [1] = {
199*4882a593Smuzhiyun .start = evt2irq(0xa20),
200*4882a593Smuzhiyun .end = evt2irq(0xa20),
201*4882a593Smuzhiyun .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
202*4882a593Smuzhiyun },
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun static struct platform_device usb0_host_device = {
206*4882a593Smuzhiyun .name = "r8a66597_hcd",
207*4882a593Smuzhiyun .id = 0,
208*4882a593Smuzhiyun .dev = {
209*4882a593Smuzhiyun .dma_mask = NULL, /* not use dma */
210*4882a593Smuzhiyun .coherent_dma_mask = 0xffffffff,
211*4882a593Smuzhiyun .platform_data = &usb0_host_data,
212*4882a593Smuzhiyun },
213*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(usb0_host_resources),
214*4882a593Smuzhiyun .resource = usb0_host_resources,
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun /* USB1 host/function */
usb1_port_power(int port,int power)218*4882a593Smuzhiyun static void usb1_port_power(int port, int power)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun gpio_set_value(GPIO_PTB5, power);
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun static struct r8a66597_platdata usb1_common_data = {
224*4882a593Smuzhiyun .on_chip = 1,
225*4882a593Smuzhiyun .port_power = usb1_port_power,
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun static struct resource usb1_common_resources[] = {
229*4882a593Smuzhiyun [0] = {
230*4882a593Smuzhiyun .start = 0xa4d90000,
231*4882a593Smuzhiyun .end = 0xa4d90124 - 1,
232*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
233*4882a593Smuzhiyun },
234*4882a593Smuzhiyun [1] = {
235*4882a593Smuzhiyun .start = evt2irq(0xa40),
236*4882a593Smuzhiyun .end = evt2irq(0xa40),
237*4882a593Smuzhiyun .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
238*4882a593Smuzhiyun },
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun static struct platform_device usb1_common_device = {
242*4882a593Smuzhiyun /* .name will be added in arch_setup */
243*4882a593Smuzhiyun .id = 1,
244*4882a593Smuzhiyun .dev = {
245*4882a593Smuzhiyun .dma_mask = NULL, /* not use dma */
246*4882a593Smuzhiyun .coherent_dma_mask = 0xffffffff,
247*4882a593Smuzhiyun .platform_data = &usb1_common_data,
248*4882a593Smuzhiyun },
249*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(usb1_common_resources),
250*4882a593Smuzhiyun .resource = usb1_common_resources,
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun /*
254*4882a593Smuzhiyun * USBHS
255*4882a593Smuzhiyun */
usbhs_get_id(struct platform_device * pdev)256*4882a593Smuzhiyun static int usbhs_get_id(struct platform_device *pdev)
257*4882a593Smuzhiyun {
258*4882a593Smuzhiyun return gpio_get_value(GPIO_PTB3);
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
usbhs_phy_reset(struct platform_device * pdev)261*4882a593Smuzhiyun static int usbhs_phy_reset(struct platform_device *pdev)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun /* enable vbus if HOST */
264*4882a593Smuzhiyun if (!gpio_get_value(GPIO_PTB3))
265*4882a593Smuzhiyun gpio_set_value(GPIO_PTB5, 1);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun return 0;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun static struct renesas_usbhs_platform_info usbhs_info = {
271*4882a593Smuzhiyun .platform_callback = {
272*4882a593Smuzhiyun .get_id = usbhs_get_id,
273*4882a593Smuzhiyun .phy_reset = usbhs_phy_reset,
274*4882a593Smuzhiyun },
275*4882a593Smuzhiyun .driver_param = {
276*4882a593Smuzhiyun .buswait_bwait = 4,
277*4882a593Smuzhiyun .detection_delay = 5,
278*4882a593Smuzhiyun .d0_tx_id = SHDMA_SLAVE_USB1D0_TX,
279*4882a593Smuzhiyun .d0_rx_id = SHDMA_SLAVE_USB1D0_RX,
280*4882a593Smuzhiyun .d1_tx_id = SHDMA_SLAVE_USB1D1_TX,
281*4882a593Smuzhiyun .d1_rx_id = SHDMA_SLAVE_USB1D1_RX,
282*4882a593Smuzhiyun },
283*4882a593Smuzhiyun };
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun static struct resource usbhs_resources[] = {
286*4882a593Smuzhiyun [0] = {
287*4882a593Smuzhiyun .start = 0xa4d90000,
288*4882a593Smuzhiyun .end = 0xa4d90124 - 1,
289*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
290*4882a593Smuzhiyun },
291*4882a593Smuzhiyun [1] = {
292*4882a593Smuzhiyun .start = evt2irq(0xa40),
293*4882a593Smuzhiyun .end = evt2irq(0xa40),
294*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
295*4882a593Smuzhiyun },
296*4882a593Smuzhiyun };
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun static struct platform_device usbhs_device = {
299*4882a593Smuzhiyun .name = "renesas_usbhs",
300*4882a593Smuzhiyun .id = 1,
301*4882a593Smuzhiyun .dev = {
302*4882a593Smuzhiyun .dma_mask = NULL, /* not use dma */
303*4882a593Smuzhiyun .coherent_dma_mask = 0xffffffff,
304*4882a593Smuzhiyun .platform_data = &usbhs_info,
305*4882a593Smuzhiyun },
306*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(usbhs_resources),
307*4882a593Smuzhiyun .resource = usbhs_resources,
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun /* LCDC and backlight */
311*4882a593Smuzhiyun static const struct fb_videomode ecovec_lcd_modes[] = {
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun .name = "Panel",
314*4882a593Smuzhiyun .xres = 800,
315*4882a593Smuzhiyun .yres = 480,
316*4882a593Smuzhiyun .left_margin = 220,
317*4882a593Smuzhiyun .right_margin = 110,
318*4882a593Smuzhiyun .hsync_len = 70,
319*4882a593Smuzhiyun .upper_margin = 20,
320*4882a593Smuzhiyun .lower_margin = 5,
321*4882a593Smuzhiyun .vsync_len = 5,
322*4882a593Smuzhiyun .sync = 0, /* hsync and vsync are active low */
323*4882a593Smuzhiyun },
324*4882a593Smuzhiyun };
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun static const struct fb_videomode ecovec_dvi_modes[] = {
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun .name = "DVI",
329*4882a593Smuzhiyun .xres = 1280,
330*4882a593Smuzhiyun .yres = 720,
331*4882a593Smuzhiyun .left_margin = 220,
332*4882a593Smuzhiyun .right_margin = 110,
333*4882a593Smuzhiyun .hsync_len = 40,
334*4882a593Smuzhiyun .upper_margin = 20,
335*4882a593Smuzhiyun .lower_margin = 5,
336*4882a593Smuzhiyun .vsync_len = 5,
337*4882a593Smuzhiyun .sync = 0, /* hsync and vsync are active low */
338*4882a593Smuzhiyun },
339*4882a593Smuzhiyun };
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun static struct sh_mobile_lcdc_info lcdc_info = {
342*4882a593Smuzhiyun .ch[0] = {
343*4882a593Smuzhiyun .interface_type = RGB18,
344*4882a593Smuzhiyun .chan = LCDC_CHAN_MAINLCD,
345*4882a593Smuzhiyun .fourcc = V4L2_PIX_FMT_RGB565,
346*4882a593Smuzhiyun .panel_cfg = { /* 7.0 inch */
347*4882a593Smuzhiyun .width = 152,
348*4882a593Smuzhiyun .height = 91,
349*4882a593Smuzhiyun },
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun };
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun static struct resource lcdc_resources[] = {
354*4882a593Smuzhiyun [0] = {
355*4882a593Smuzhiyun .name = "LCDC",
356*4882a593Smuzhiyun .start = 0xfe940000,
357*4882a593Smuzhiyun .end = 0xfe942fff,
358*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
359*4882a593Smuzhiyun },
360*4882a593Smuzhiyun [1] = {
361*4882a593Smuzhiyun .start = evt2irq(0xf40),
362*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
363*4882a593Smuzhiyun },
364*4882a593Smuzhiyun };
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun static struct platform_device lcdc_device = {
367*4882a593Smuzhiyun .name = "sh_mobile_lcdc_fb",
368*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(lcdc_resources),
369*4882a593Smuzhiyun .resource = lcdc_resources,
370*4882a593Smuzhiyun .dev = {
371*4882a593Smuzhiyun .platform_data = &lcdc_info,
372*4882a593Smuzhiyun },
373*4882a593Smuzhiyun };
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun static struct gpiod_lookup_table gpio_backlight_lookup = {
376*4882a593Smuzhiyun .dev_id = "gpio-backlight.0",
377*4882a593Smuzhiyun .table = {
378*4882a593Smuzhiyun GPIO_LOOKUP("sh7724_pfc", GPIO_PTR1, NULL, GPIO_ACTIVE_HIGH),
379*4882a593Smuzhiyun { }
380*4882a593Smuzhiyun },
381*4882a593Smuzhiyun };
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun static struct property_entry gpio_backlight_props[] = {
384*4882a593Smuzhiyun PROPERTY_ENTRY_BOOL("default-on"),
385*4882a593Smuzhiyun { }
386*4882a593Smuzhiyun };
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun static struct gpio_backlight_platform_data gpio_backlight_data = {
389*4882a593Smuzhiyun .fbdev = &lcdc_device.dev,
390*4882a593Smuzhiyun };
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun static const struct platform_device_info gpio_backlight_device_info = {
393*4882a593Smuzhiyun .name = "gpio-backlight",
394*4882a593Smuzhiyun .data = &gpio_backlight_data,
395*4882a593Smuzhiyun .size_data = sizeof(gpio_backlight_data),
396*4882a593Smuzhiyun .properties = gpio_backlight_props,
397*4882a593Smuzhiyun };
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun static struct platform_device *gpio_backlight_device;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun /* CEU0 */
402*4882a593Smuzhiyun static struct ceu_platform_data ceu0_pdata = {
403*4882a593Smuzhiyun .num_subdevs = 2,
404*4882a593Smuzhiyun .subdevs = {
405*4882a593Smuzhiyun { /* [0] = mt9t112 */
406*4882a593Smuzhiyun .flags = 0,
407*4882a593Smuzhiyun .bus_width = 8,
408*4882a593Smuzhiyun .bus_shift = 0,
409*4882a593Smuzhiyun .i2c_adapter_id = 0,
410*4882a593Smuzhiyun .i2c_address = 0x3c,
411*4882a593Smuzhiyun },
412*4882a593Smuzhiyun { /* [1] = tw9910 */
413*4882a593Smuzhiyun .flags = 0,
414*4882a593Smuzhiyun .bus_width = 8,
415*4882a593Smuzhiyun .bus_shift = 0,
416*4882a593Smuzhiyun .i2c_adapter_id = 0,
417*4882a593Smuzhiyun .i2c_address = 0x45,
418*4882a593Smuzhiyun },
419*4882a593Smuzhiyun },
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun static struct resource ceu0_resources[] = {
423*4882a593Smuzhiyun [0] = {
424*4882a593Smuzhiyun .name = "CEU0",
425*4882a593Smuzhiyun .start = 0xfe910000,
426*4882a593Smuzhiyun .end = 0xfe91009f,
427*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
428*4882a593Smuzhiyun },
429*4882a593Smuzhiyun [1] = {
430*4882a593Smuzhiyun .start = evt2irq(0x880),
431*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
432*4882a593Smuzhiyun },
433*4882a593Smuzhiyun };
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun static struct platform_device ceu0_device = {
436*4882a593Smuzhiyun .name = "renesas-ceu",
437*4882a593Smuzhiyun .id = 0, /* ceu.0 */
438*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ceu0_resources),
439*4882a593Smuzhiyun .resource = ceu0_resources,
440*4882a593Smuzhiyun .dev = {
441*4882a593Smuzhiyun .platform_data = &ceu0_pdata,
442*4882a593Smuzhiyun },
443*4882a593Smuzhiyun };
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun /* CEU1 */
446*4882a593Smuzhiyun static struct ceu_platform_data ceu1_pdata = {
447*4882a593Smuzhiyun .num_subdevs = 1,
448*4882a593Smuzhiyun .subdevs = {
449*4882a593Smuzhiyun { /* [0] = mt9t112 */
450*4882a593Smuzhiyun .flags = 0,
451*4882a593Smuzhiyun .bus_width = 8,
452*4882a593Smuzhiyun .bus_shift = 0,
453*4882a593Smuzhiyun .i2c_adapter_id = 1,
454*4882a593Smuzhiyun .i2c_address = 0x3c,
455*4882a593Smuzhiyun },
456*4882a593Smuzhiyun },
457*4882a593Smuzhiyun };
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun static struct resource ceu1_resources[] = {
460*4882a593Smuzhiyun [0] = {
461*4882a593Smuzhiyun .name = "CEU1",
462*4882a593Smuzhiyun .start = 0xfe914000,
463*4882a593Smuzhiyun .end = 0xfe91409f,
464*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
465*4882a593Smuzhiyun },
466*4882a593Smuzhiyun [1] = {
467*4882a593Smuzhiyun .start = evt2irq(0x9e0),
468*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
469*4882a593Smuzhiyun },
470*4882a593Smuzhiyun };
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun static struct platform_device ceu1_device = {
473*4882a593Smuzhiyun .name = "renesas-ceu",
474*4882a593Smuzhiyun .id = 1, /* ceu.1 */
475*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ceu1_resources),
476*4882a593Smuzhiyun .resource = ceu1_resources,
477*4882a593Smuzhiyun .dev = {
478*4882a593Smuzhiyun .platform_data = &ceu1_pdata,
479*4882a593Smuzhiyun },
480*4882a593Smuzhiyun };
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun /* Power up/down GPIOs for camera devices and video decoder */
483*4882a593Smuzhiyun static struct gpiod_lookup_table tw9910_gpios = {
484*4882a593Smuzhiyun .dev_id = "0-0045",
485*4882a593Smuzhiyun .table = {
486*4882a593Smuzhiyun GPIO_LOOKUP("sh7724_pfc", GPIO_PTU2, "pdn", GPIO_ACTIVE_HIGH),
487*4882a593Smuzhiyun },
488*4882a593Smuzhiyun };
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun static struct gpiod_lookup_table mt9t112_0_gpios = {
491*4882a593Smuzhiyun .dev_id = "0-003c",
492*4882a593Smuzhiyun .table = {
493*4882a593Smuzhiyun GPIO_LOOKUP("sh7724_pfc", GPIO_PTA3, "standby",
494*4882a593Smuzhiyun GPIO_ACTIVE_HIGH),
495*4882a593Smuzhiyun },
496*4882a593Smuzhiyun };
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun static struct gpiod_lookup_table mt9t112_1_gpios = {
499*4882a593Smuzhiyun .dev_id = "1-003c",
500*4882a593Smuzhiyun .table = {
501*4882a593Smuzhiyun GPIO_LOOKUP("sh7724_pfc", GPIO_PTA4, "standby",
502*4882a593Smuzhiyun GPIO_ACTIVE_HIGH),
503*4882a593Smuzhiyun },
504*4882a593Smuzhiyun };
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun /* I2C device */
507*4882a593Smuzhiyun static struct tw9910_video_info tw9910_info = {
508*4882a593Smuzhiyun .buswidth = 8,
509*4882a593Smuzhiyun .mpout = TW9910_MPO_FIELD,
510*4882a593Smuzhiyun };
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun static struct mt9t112_platform_data mt9t112_0_pdata = {
513*4882a593Smuzhiyun .flags = MT9T112_FLAG_PCLK_RISING_EDGE,
514*4882a593Smuzhiyun .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
515*4882a593Smuzhiyun };
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun static struct mt9t112_platform_data mt9t112_1_pdata = {
518*4882a593Smuzhiyun .flags = MT9T112_FLAG_PCLK_RISING_EDGE,
519*4882a593Smuzhiyun .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
520*4882a593Smuzhiyun };
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun static struct i2c_board_info i2c0_devices[] = {
523*4882a593Smuzhiyun {
524*4882a593Smuzhiyun I2C_BOARD_INFO("da7210", 0x1a),
525*4882a593Smuzhiyun },
526*4882a593Smuzhiyun {
527*4882a593Smuzhiyun I2C_BOARD_INFO("tw9910", 0x45),
528*4882a593Smuzhiyun .platform_data = &tw9910_info,
529*4882a593Smuzhiyun },
530*4882a593Smuzhiyun {
531*4882a593Smuzhiyun /* 1st camera */
532*4882a593Smuzhiyun I2C_BOARD_INFO("mt9t112", 0x3c),
533*4882a593Smuzhiyun .platform_data = &mt9t112_0_pdata,
534*4882a593Smuzhiyun },
535*4882a593Smuzhiyun };
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun static struct i2c_board_info i2c1_devices[] = {
538*4882a593Smuzhiyun {
539*4882a593Smuzhiyun I2C_BOARD_INFO("r2025sd", 0x32),
540*4882a593Smuzhiyun },
541*4882a593Smuzhiyun {
542*4882a593Smuzhiyun I2C_BOARD_INFO("lis3lv02d", 0x1c),
543*4882a593Smuzhiyun .irq = evt2irq(0x620),
544*4882a593Smuzhiyun },
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun /* 2nd camera */
547*4882a593Smuzhiyun I2C_BOARD_INFO("mt9t112", 0x3c),
548*4882a593Smuzhiyun .platform_data = &mt9t112_1_pdata,
549*4882a593Smuzhiyun },
550*4882a593Smuzhiyun };
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun /* KEYSC */
553*4882a593Smuzhiyun static struct sh_keysc_info keysc_info = {
554*4882a593Smuzhiyun .mode = SH_KEYSC_MODE_1,
555*4882a593Smuzhiyun .scan_timing = 3,
556*4882a593Smuzhiyun .delay = 50,
557*4882a593Smuzhiyun .kycr2_delay = 100,
558*4882a593Smuzhiyun .keycodes = { KEY_1, 0, 0, 0, 0,
559*4882a593Smuzhiyun KEY_2, 0, 0, 0, 0,
560*4882a593Smuzhiyun KEY_3, 0, 0, 0, 0,
561*4882a593Smuzhiyun KEY_4, 0, 0, 0, 0,
562*4882a593Smuzhiyun KEY_5, 0, 0, 0, 0,
563*4882a593Smuzhiyun KEY_6, 0, 0, 0, 0, },
564*4882a593Smuzhiyun };
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun static struct resource keysc_resources[] = {
567*4882a593Smuzhiyun [0] = {
568*4882a593Smuzhiyun .name = "KEYSC",
569*4882a593Smuzhiyun .start = 0x044b0000,
570*4882a593Smuzhiyun .end = 0x044b000f,
571*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
572*4882a593Smuzhiyun },
573*4882a593Smuzhiyun [1] = {
574*4882a593Smuzhiyun .start = evt2irq(0xbe0),
575*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
576*4882a593Smuzhiyun },
577*4882a593Smuzhiyun };
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun static struct platform_device keysc_device = {
580*4882a593Smuzhiyun .name = "sh_keysc",
581*4882a593Smuzhiyun .id = 0, /* keysc0 clock */
582*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(keysc_resources),
583*4882a593Smuzhiyun .resource = keysc_resources,
584*4882a593Smuzhiyun .dev = {
585*4882a593Smuzhiyun .platform_data = &keysc_info,
586*4882a593Smuzhiyun },
587*4882a593Smuzhiyun };
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun /* TouchScreen */
590*4882a593Smuzhiyun #define IRQ0 evt2irq(0x600)
591*4882a593Smuzhiyun
ts_get_pendown_state(struct device * dev)592*4882a593Smuzhiyun static int ts_get_pendown_state(struct device *dev)
593*4882a593Smuzhiyun {
594*4882a593Smuzhiyun int val = 0;
595*4882a593Smuzhiyun gpio_free(GPIO_FN_INTC_IRQ0);
596*4882a593Smuzhiyun gpio_request(GPIO_PTZ0, NULL);
597*4882a593Smuzhiyun gpio_direction_input(GPIO_PTZ0);
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun val = gpio_get_value(GPIO_PTZ0);
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun gpio_free(GPIO_PTZ0);
602*4882a593Smuzhiyun gpio_request(GPIO_FN_INTC_IRQ0, NULL);
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun return val ? 0 : 1;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun
ts_init(void)607*4882a593Smuzhiyun static int ts_init(void)
608*4882a593Smuzhiyun {
609*4882a593Smuzhiyun gpio_request(GPIO_FN_INTC_IRQ0, NULL);
610*4882a593Smuzhiyun return 0;
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun static struct tsc2007_platform_data tsc2007_info = {
614*4882a593Smuzhiyun .model = 2007,
615*4882a593Smuzhiyun .x_plate_ohms = 180,
616*4882a593Smuzhiyun .get_pendown_state = ts_get_pendown_state,
617*4882a593Smuzhiyun .init_platform_hw = ts_init,
618*4882a593Smuzhiyun };
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun static struct i2c_board_info ts_i2c_clients = {
621*4882a593Smuzhiyun I2C_BOARD_INFO("tsc2007", 0x48),
622*4882a593Smuzhiyun .type = "tsc2007",
623*4882a593Smuzhiyun .platform_data = &tsc2007_info,
624*4882a593Smuzhiyun .irq = IRQ0,
625*4882a593Smuzhiyun };
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun static struct regulator_consumer_supply cn12_power_consumers[] =
628*4882a593Smuzhiyun {
629*4882a593Smuzhiyun REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
630*4882a593Smuzhiyun REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
631*4882a593Smuzhiyun REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
632*4882a593Smuzhiyun REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
633*4882a593Smuzhiyun };
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun static struct regulator_init_data cn12_power_init_data = {
636*4882a593Smuzhiyun .constraints = {
637*4882a593Smuzhiyun .valid_ops_mask = REGULATOR_CHANGE_STATUS,
638*4882a593Smuzhiyun },
639*4882a593Smuzhiyun .num_consumer_supplies = ARRAY_SIZE(cn12_power_consumers),
640*4882a593Smuzhiyun .consumer_supplies = cn12_power_consumers,
641*4882a593Smuzhiyun };
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun static struct fixed_voltage_config cn12_power_info = {
644*4882a593Smuzhiyun .supply_name = "CN12 SD/MMC Vdd",
645*4882a593Smuzhiyun .microvolts = 3300000,
646*4882a593Smuzhiyun .init_data = &cn12_power_init_data,
647*4882a593Smuzhiyun };
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun static struct platform_device cn12_power = {
650*4882a593Smuzhiyun .name = "reg-fixed-voltage",
651*4882a593Smuzhiyun .id = 0,
652*4882a593Smuzhiyun .dev = {
653*4882a593Smuzhiyun .platform_data = &cn12_power_info,
654*4882a593Smuzhiyun },
655*4882a593Smuzhiyun };
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun static struct gpiod_lookup_table cn12_power_gpiod_table = {
658*4882a593Smuzhiyun .dev_id = "reg-fixed-voltage.0",
659*4882a593Smuzhiyun .table = {
660*4882a593Smuzhiyun /* Offset 7 on port B */
661*4882a593Smuzhiyun GPIO_LOOKUP("sh7724_pfc", GPIO_PTB7,
662*4882a593Smuzhiyun NULL, GPIO_ACTIVE_HIGH),
663*4882a593Smuzhiyun { },
664*4882a593Smuzhiyun },
665*4882a593Smuzhiyun };
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun #if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
668*4882a593Smuzhiyun /* SDHI0 */
669*4882a593Smuzhiyun static struct regulator_consumer_supply sdhi0_power_consumers[] =
670*4882a593Smuzhiyun {
671*4882a593Smuzhiyun REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
672*4882a593Smuzhiyun REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
673*4882a593Smuzhiyun };
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun static struct regulator_init_data sdhi0_power_init_data = {
676*4882a593Smuzhiyun .constraints = {
677*4882a593Smuzhiyun .valid_ops_mask = REGULATOR_CHANGE_STATUS,
678*4882a593Smuzhiyun },
679*4882a593Smuzhiyun .num_consumer_supplies = ARRAY_SIZE(sdhi0_power_consumers),
680*4882a593Smuzhiyun .consumer_supplies = sdhi0_power_consumers,
681*4882a593Smuzhiyun };
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun static struct fixed_voltage_config sdhi0_power_info = {
684*4882a593Smuzhiyun .supply_name = "CN11 SD/MMC Vdd",
685*4882a593Smuzhiyun .microvolts = 3300000,
686*4882a593Smuzhiyun .init_data = &sdhi0_power_init_data,
687*4882a593Smuzhiyun };
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun static struct platform_device sdhi0_power = {
690*4882a593Smuzhiyun .name = "reg-fixed-voltage",
691*4882a593Smuzhiyun .id = 1,
692*4882a593Smuzhiyun .dev = {
693*4882a593Smuzhiyun .platform_data = &sdhi0_power_info,
694*4882a593Smuzhiyun },
695*4882a593Smuzhiyun };
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun static struct gpiod_lookup_table sdhi0_power_gpiod_table = {
698*4882a593Smuzhiyun .dev_id = "reg-fixed-voltage.1",
699*4882a593Smuzhiyun .table = {
700*4882a593Smuzhiyun /* Offset 6 on port B */
701*4882a593Smuzhiyun GPIO_LOOKUP("sh7724_pfc", GPIO_PTB6,
702*4882a593Smuzhiyun NULL, GPIO_ACTIVE_HIGH),
703*4882a593Smuzhiyun { },
704*4882a593Smuzhiyun },
705*4882a593Smuzhiyun };
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun static struct gpiod_lookup_table sdhi0_gpio_table = {
708*4882a593Smuzhiyun .dev_id = "sh_mobile_sdhi.0",
709*4882a593Smuzhiyun .table = {
710*4882a593Smuzhiyun /* Card detect */
711*4882a593Smuzhiyun GPIO_LOOKUP("sh7724_pfc", GPIO_PTY7, "cd", GPIO_ACTIVE_LOW),
712*4882a593Smuzhiyun { },
713*4882a593Smuzhiyun },
714*4882a593Smuzhiyun };
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun static struct tmio_mmc_data sdhi0_info = {
717*4882a593Smuzhiyun .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
718*4882a593Smuzhiyun .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
719*4882a593Smuzhiyun .capabilities = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD |
720*4882a593Smuzhiyun MMC_CAP_NEEDS_POLL,
721*4882a593Smuzhiyun };
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun static struct resource sdhi0_resources[] = {
724*4882a593Smuzhiyun [0] = {
725*4882a593Smuzhiyun .name = "SDHI0",
726*4882a593Smuzhiyun .start = 0x04ce0000,
727*4882a593Smuzhiyun .end = 0x04ce00ff,
728*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
729*4882a593Smuzhiyun },
730*4882a593Smuzhiyun [1] = {
731*4882a593Smuzhiyun .start = evt2irq(0xe80),
732*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
733*4882a593Smuzhiyun },
734*4882a593Smuzhiyun };
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun static struct platform_device sdhi0_device = {
737*4882a593Smuzhiyun .name = "sh_mobile_sdhi",
738*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(sdhi0_resources),
739*4882a593Smuzhiyun .resource = sdhi0_resources,
740*4882a593Smuzhiyun .id = 0,
741*4882a593Smuzhiyun .dev = {
742*4882a593Smuzhiyun .platform_data = &sdhi0_info,
743*4882a593Smuzhiyun },
744*4882a593Smuzhiyun };
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
747*4882a593Smuzhiyun /* SDHI1 */
748*4882a593Smuzhiyun static struct tmio_mmc_data sdhi1_info = {
749*4882a593Smuzhiyun .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI1_TX,
750*4882a593Smuzhiyun .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI1_RX,
751*4882a593Smuzhiyun .capabilities = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD |
752*4882a593Smuzhiyun MMC_CAP_NEEDS_POLL,
753*4882a593Smuzhiyun };
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun static struct gpiod_lookup_table sdhi1_gpio_table = {
756*4882a593Smuzhiyun .dev_id = "sh_mobile_sdhi.1",
757*4882a593Smuzhiyun .table = {
758*4882a593Smuzhiyun /* Card detect */
759*4882a593Smuzhiyun GPIO_LOOKUP("sh7724_pfc", GPIO_PTW7, "cd", GPIO_ACTIVE_LOW),
760*4882a593Smuzhiyun { },
761*4882a593Smuzhiyun },
762*4882a593Smuzhiyun };
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun static struct resource sdhi1_resources[] = {
765*4882a593Smuzhiyun [0] = {
766*4882a593Smuzhiyun .name = "SDHI1",
767*4882a593Smuzhiyun .start = 0x04cf0000,
768*4882a593Smuzhiyun .end = 0x04cf00ff,
769*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
770*4882a593Smuzhiyun },
771*4882a593Smuzhiyun [1] = {
772*4882a593Smuzhiyun .start = evt2irq(0x4e0),
773*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
774*4882a593Smuzhiyun },
775*4882a593Smuzhiyun };
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun static struct platform_device sdhi1_device = {
778*4882a593Smuzhiyun .name = "sh_mobile_sdhi",
779*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(sdhi1_resources),
780*4882a593Smuzhiyun .resource = sdhi1_resources,
781*4882a593Smuzhiyun .id = 1,
782*4882a593Smuzhiyun .dev = {
783*4882a593Smuzhiyun .platform_data = &sdhi1_info,
784*4882a593Smuzhiyun },
785*4882a593Smuzhiyun };
786*4882a593Smuzhiyun #endif /* CONFIG_MMC_SH_MMCIF */
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun #else
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun /* MMC SPI */
mmc_spi_setpower(struct device * dev,unsigned int maskval)791*4882a593Smuzhiyun static void mmc_spi_setpower(struct device *dev, unsigned int maskval)
792*4882a593Smuzhiyun {
793*4882a593Smuzhiyun gpio_set_value(GPIO_PTB6, maskval ? 1 : 0);
794*4882a593Smuzhiyun }
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun static struct mmc_spi_platform_data mmc_spi_info = {
797*4882a593Smuzhiyun .caps = MMC_CAP_NEEDS_POLL,
798*4882a593Smuzhiyun .caps2 = MMC_CAP2_RO_ACTIVE_HIGH,
799*4882a593Smuzhiyun .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3.3V only */
800*4882a593Smuzhiyun .setpower = mmc_spi_setpower,
801*4882a593Smuzhiyun };
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun static struct gpiod_lookup_table mmc_spi_gpio_table = {
804*4882a593Smuzhiyun .dev_id = "mmc_spi.0", /* device "mmc_spi" @ CS0 */
805*4882a593Smuzhiyun .table = {
806*4882a593Smuzhiyun /* Card detect */
807*4882a593Smuzhiyun GPIO_LOOKUP_IDX("sh7724_pfc", GPIO_PTY7, NULL, 0,
808*4882a593Smuzhiyun GPIO_ACTIVE_LOW),
809*4882a593Smuzhiyun /* Write protect */
810*4882a593Smuzhiyun GPIO_LOOKUP_IDX("sh7724_pfc", GPIO_PTY6, NULL, 1,
811*4882a593Smuzhiyun GPIO_ACTIVE_HIGH),
812*4882a593Smuzhiyun { },
813*4882a593Smuzhiyun },
814*4882a593Smuzhiyun };
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun static struct spi_board_info spi_bus[] = {
817*4882a593Smuzhiyun {
818*4882a593Smuzhiyun .modalias = "mmc_spi",
819*4882a593Smuzhiyun .platform_data = &mmc_spi_info,
820*4882a593Smuzhiyun .max_speed_hz = 5000000,
821*4882a593Smuzhiyun .mode = SPI_MODE_0,
822*4882a593Smuzhiyun },
823*4882a593Smuzhiyun };
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun /* MSIOF0 */
826*4882a593Smuzhiyun static struct sh_msiof_spi_info msiof0_data = {
827*4882a593Smuzhiyun .num_chipselect = 1,
828*4882a593Smuzhiyun };
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun static struct resource msiof0_resources[] = {
831*4882a593Smuzhiyun [0] = {
832*4882a593Smuzhiyun .name = "MSIOF0",
833*4882a593Smuzhiyun .start = 0xa4c40000,
834*4882a593Smuzhiyun .end = 0xa4c40063,
835*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
836*4882a593Smuzhiyun },
837*4882a593Smuzhiyun [1] = {
838*4882a593Smuzhiyun .start = evt2irq(0xc80),
839*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
840*4882a593Smuzhiyun },
841*4882a593Smuzhiyun };
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun static struct platform_device msiof0_device = {
844*4882a593Smuzhiyun .name = "spi_sh_msiof",
845*4882a593Smuzhiyun .id = 0, /* MSIOF0 */
846*4882a593Smuzhiyun .dev = {
847*4882a593Smuzhiyun .platform_data = &msiof0_data,
848*4882a593Smuzhiyun },
849*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(msiof0_resources),
850*4882a593Smuzhiyun .resource = msiof0_resources,
851*4882a593Smuzhiyun };
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun static struct gpiod_lookup_table msiof_gpio_table = {
854*4882a593Smuzhiyun .dev_id = "spi_sh_msiof.0",
855*4882a593Smuzhiyun .table = {
856*4882a593Smuzhiyun GPIO_LOOKUP("sh7724_pfc", GPIO_PTM4, "cs", GPIO_ACTIVE_HIGH),
857*4882a593Smuzhiyun { },
858*4882a593Smuzhiyun },
859*4882a593Smuzhiyun };
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun #endif
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun /* FSI */
864*4882a593Smuzhiyun static struct resource fsi_resources[] = {
865*4882a593Smuzhiyun [0] = {
866*4882a593Smuzhiyun .name = "FSI",
867*4882a593Smuzhiyun .start = 0xFE3C0000,
868*4882a593Smuzhiyun .end = 0xFE3C021d,
869*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
870*4882a593Smuzhiyun },
871*4882a593Smuzhiyun [1] = {
872*4882a593Smuzhiyun .start = evt2irq(0xf80),
873*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
874*4882a593Smuzhiyun },
875*4882a593Smuzhiyun };
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun static struct platform_device fsi_device = {
878*4882a593Smuzhiyun .name = "sh_fsi",
879*4882a593Smuzhiyun .id = 0,
880*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(fsi_resources),
881*4882a593Smuzhiyun .resource = fsi_resources,
882*4882a593Smuzhiyun };
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun static struct asoc_simple_card_info fsi_da7210_info = {
885*4882a593Smuzhiyun .name = "DA7210",
886*4882a593Smuzhiyun .card = "FSIB-DA7210",
887*4882a593Smuzhiyun .codec = "da7210.0-001a",
888*4882a593Smuzhiyun .platform = "sh_fsi.0",
889*4882a593Smuzhiyun .daifmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
890*4882a593Smuzhiyun .cpu_dai = {
891*4882a593Smuzhiyun .name = "fsib-dai",
892*4882a593Smuzhiyun },
893*4882a593Smuzhiyun .codec_dai = {
894*4882a593Smuzhiyun .name = "da7210-hifi",
895*4882a593Smuzhiyun },
896*4882a593Smuzhiyun };
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun static struct platform_device fsi_da7210_device = {
899*4882a593Smuzhiyun .name = "asoc-simple-card",
900*4882a593Smuzhiyun .dev = {
901*4882a593Smuzhiyun .platform_data = &fsi_da7210_info,
902*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
903*4882a593Smuzhiyun .dma_mask = &fsi_da7210_device.dev.coherent_dma_mask,
904*4882a593Smuzhiyun },
905*4882a593Smuzhiyun };
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun /* IrDA */
909*4882a593Smuzhiyun static struct resource irda_resources[] = {
910*4882a593Smuzhiyun [0] = {
911*4882a593Smuzhiyun .name = "IrDA",
912*4882a593Smuzhiyun .start = 0xA45D0000,
913*4882a593Smuzhiyun .end = 0xA45D0049,
914*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
915*4882a593Smuzhiyun },
916*4882a593Smuzhiyun [1] = {
917*4882a593Smuzhiyun .start = evt2irq(0x480),
918*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
919*4882a593Smuzhiyun },
920*4882a593Smuzhiyun };
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun static struct platform_device irda_device = {
923*4882a593Smuzhiyun .name = "sh_sir",
924*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(irda_resources),
925*4882a593Smuzhiyun .resource = irda_resources,
926*4882a593Smuzhiyun };
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun #include <media/i2c/ak881x.h>
929*4882a593Smuzhiyun #include <media/drv-intf/sh_vou.h>
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun static struct ak881x_pdata ak881x_pdata = {
932*4882a593Smuzhiyun .flags = AK881X_IF_MODE_SLAVE,
933*4882a593Smuzhiyun };
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun static struct i2c_board_info ak8813 = {
936*4882a593Smuzhiyun I2C_BOARD_INFO("ak8813", 0x20),
937*4882a593Smuzhiyun .platform_data = &ak881x_pdata,
938*4882a593Smuzhiyun };
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun static struct sh_vou_pdata sh_vou_pdata = {
941*4882a593Smuzhiyun .bus_fmt = SH_VOU_BUS_8BIT,
942*4882a593Smuzhiyun .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
943*4882a593Smuzhiyun .board_info = &ak8813,
944*4882a593Smuzhiyun .i2c_adap = 0,
945*4882a593Smuzhiyun };
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun static struct resource sh_vou_resources[] = {
948*4882a593Smuzhiyun [0] = {
949*4882a593Smuzhiyun .start = 0xfe960000,
950*4882a593Smuzhiyun .end = 0xfe962043,
951*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
952*4882a593Smuzhiyun },
953*4882a593Smuzhiyun [1] = {
954*4882a593Smuzhiyun .start = evt2irq(0x8e0),
955*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
956*4882a593Smuzhiyun },
957*4882a593Smuzhiyun };
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun static struct platform_device vou_device = {
960*4882a593Smuzhiyun .name = "sh-vou",
961*4882a593Smuzhiyun .id = -1,
962*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(sh_vou_resources),
963*4882a593Smuzhiyun .resource = sh_vou_resources,
964*4882a593Smuzhiyun .dev = {
965*4882a593Smuzhiyun .platform_data = &sh_vou_pdata,
966*4882a593Smuzhiyun },
967*4882a593Smuzhiyun };
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun #if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
970*4882a593Smuzhiyun /* SH_MMCIF */
971*4882a593Smuzhiyun static struct resource sh_mmcif_resources[] = {
972*4882a593Smuzhiyun [0] = {
973*4882a593Smuzhiyun .name = "SH_MMCIF",
974*4882a593Smuzhiyun .start = 0xA4CA0000,
975*4882a593Smuzhiyun .end = 0xA4CA00FF,
976*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
977*4882a593Smuzhiyun },
978*4882a593Smuzhiyun [1] = {
979*4882a593Smuzhiyun /* MMC2I */
980*4882a593Smuzhiyun .start = evt2irq(0x5a0),
981*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
982*4882a593Smuzhiyun },
983*4882a593Smuzhiyun [2] = {
984*4882a593Smuzhiyun /* MMC3I */
985*4882a593Smuzhiyun .start = evt2irq(0x5c0),
986*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
987*4882a593Smuzhiyun },
988*4882a593Smuzhiyun };
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun static struct sh_mmcif_plat_data sh_mmcif_plat = {
991*4882a593Smuzhiyun .sup_pclk = 0, /* SH7724: Max Pclk/2 */
992*4882a593Smuzhiyun .caps = MMC_CAP_4_BIT_DATA |
993*4882a593Smuzhiyun MMC_CAP_8_BIT_DATA |
994*4882a593Smuzhiyun MMC_CAP_NEEDS_POLL,
995*4882a593Smuzhiyun .ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
996*4882a593Smuzhiyun };
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun static struct platform_device sh_mmcif_device = {
999*4882a593Smuzhiyun .name = "sh_mmcif",
1000*4882a593Smuzhiyun .id = 0,
1001*4882a593Smuzhiyun .dev = {
1002*4882a593Smuzhiyun .platform_data = &sh_mmcif_plat,
1003*4882a593Smuzhiyun },
1004*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(sh_mmcif_resources),
1005*4882a593Smuzhiyun .resource = sh_mmcif_resources,
1006*4882a593Smuzhiyun };
1007*4882a593Smuzhiyun #endif
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun static struct platform_device *ecovec_ceu_devices[] __initdata = {
1010*4882a593Smuzhiyun &ceu0_device,
1011*4882a593Smuzhiyun &ceu1_device,
1012*4882a593Smuzhiyun };
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun static struct platform_device *ecovec_devices[] __initdata = {
1015*4882a593Smuzhiyun &heartbeat_device,
1016*4882a593Smuzhiyun &nor_flash_device,
1017*4882a593Smuzhiyun &sh_eth_device,
1018*4882a593Smuzhiyun &usb0_host_device,
1019*4882a593Smuzhiyun &usb1_common_device,
1020*4882a593Smuzhiyun &usbhs_device,
1021*4882a593Smuzhiyun &lcdc_device,
1022*4882a593Smuzhiyun &keysc_device,
1023*4882a593Smuzhiyun &cn12_power,
1024*4882a593Smuzhiyun #if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
1025*4882a593Smuzhiyun &sdhi0_power,
1026*4882a593Smuzhiyun &sdhi0_device,
1027*4882a593Smuzhiyun #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
1028*4882a593Smuzhiyun &sdhi1_device,
1029*4882a593Smuzhiyun #endif
1030*4882a593Smuzhiyun #else
1031*4882a593Smuzhiyun &msiof0_device,
1032*4882a593Smuzhiyun #endif
1033*4882a593Smuzhiyun &fsi_device,
1034*4882a593Smuzhiyun &fsi_da7210_device,
1035*4882a593Smuzhiyun &irda_device,
1036*4882a593Smuzhiyun &vou_device,
1037*4882a593Smuzhiyun #if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
1038*4882a593Smuzhiyun &sh_mmcif_device,
1039*4882a593Smuzhiyun #endif
1040*4882a593Smuzhiyun };
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun #ifdef CONFIG_I2C
1043*4882a593Smuzhiyun #define EEPROM_ADDR 0x50
mac_read(struct i2c_adapter * a,u8 command)1044*4882a593Smuzhiyun static u8 mac_read(struct i2c_adapter *a, u8 command)
1045*4882a593Smuzhiyun {
1046*4882a593Smuzhiyun struct i2c_msg msg[2];
1047*4882a593Smuzhiyun u8 buf;
1048*4882a593Smuzhiyun int ret;
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun msg[0].addr = EEPROM_ADDR;
1051*4882a593Smuzhiyun msg[0].flags = 0;
1052*4882a593Smuzhiyun msg[0].len = 1;
1053*4882a593Smuzhiyun msg[0].buf = &command;
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun msg[1].addr = EEPROM_ADDR;
1056*4882a593Smuzhiyun msg[1].flags = I2C_M_RD;
1057*4882a593Smuzhiyun msg[1].len = 1;
1058*4882a593Smuzhiyun msg[1].buf = &buf;
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun ret = i2c_transfer(a, msg, 2);
1061*4882a593Smuzhiyun if (ret < 0) {
1062*4882a593Smuzhiyun printk(KERN_ERR "error %d\n", ret);
1063*4882a593Smuzhiyun buf = 0xff;
1064*4882a593Smuzhiyun }
1065*4882a593Smuzhiyun
1066*4882a593Smuzhiyun return buf;
1067*4882a593Smuzhiyun }
1068*4882a593Smuzhiyun
sh_eth_init(struct sh_eth_plat_data * pd)1069*4882a593Smuzhiyun static void __init sh_eth_init(struct sh_eth_plat_data *pd)
1070*4882a593Smuzhiyun {
1071*4882a593Smuzhiyun struct i2c_adapter *a = i2c_get_adapter(1);
1072*4882a593Smuzhiyun int i;
1073*4882a593Smuzhiyun
1074*4882a593Smuzhiyun if (!a) {
1075*4882a593Smuzhiyun pr_err("can not get I2C 1\n");
1076*4882a593Smuzhiyun return;
1077*4882a593Smuzhiyun }
1078*4882a593Smuzhiyun
1079*4882a593Smuzhiyun /* read MAC address from EEPROM */
1080*4882a593Smuzhiyun for (i = 0; i < sizeof(pd->mac_addr); i++) {
1081*4882a593Smuzhiyun pd->mac_addr[i] = mac_read(a, 0x10 + i);
1082*4882a593Smuzhiyun msleep(10);
1083*4882a593Smuzhiyun }
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun i2c_put_adapter(a);
1086*4882a593Smuzhiyun }
1087*4882a593Smuzhiyun #else
sh_eth_init(struct sh_eth_plat_data * pd)1088*4882a593Smuzhiyun static void __init sh_eth_init(struct sh_eth_plat_data *pd)
1089*4882a593Smuzhiyun {
1090*4882a593Smuzhiyun pr_err("unable to read sh_eth MAC address\n");
1091*4882a593Smuzhiyun }
1092*4882a593Smuzhiyun #endif
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun #define PORT_HIZA 0xA4050158
1095*4882a593Smuzhiyun #define IODRIVEA 0xA405018A
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun extern char ecovec24_sdram_enter_start;
1098*4882a593Smuzhiyun extern char ecovec24_sdram_enter_end;
1099*4882a593Smuzhiyun extern char ecovec24_sdram_leave_start;
1100*4882a593Smuzhiyun extern char ecovec24_sdram_leave_end;
1101*4882a593Smuzhiyun
arch_setup(void)1102*4882a593Smuzhiyun static int __init arch_setup(void)
1103*4882a593Smuzhiyun {
1104*4882a593Smuzhiyun struct clk *clk;
1105*4882a593Smuzhiyun bool cn12_enabled = false;
1106*4882a593Smuzhiyun
1107*4882a593Smuzhiyun /* register board specific self-refresh code */
1108*4882a593Smuzhiyun sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
1109*4882a593Smuzhiyun SUSP_SH_RSTANDBY,
1110*4882a593Smuzhiyun &ecovec24_sdram_enter_start,
1111*4882a593Smuzhiyun &ecovec24_sdram_enter_end,
1112*4882a593Smuzhiyun &ecovec24_sdram_leave_start,
1113*4882a593Smuzhiyun &ecovec24_sdram_leave_end);
1114*4882a593Smuzhiyun
1115*4882a593Smuzhiyun /* enable STATUS0, STATUS2 and PDSTATUS */
1116*4882a593Smuzhiyun gpio_request(GPIO_FN_STATUS0, NULL);
1117*4882a593Smuzhiyun gpio_request(GPIO_FN_STATUS2, NULL);
1118*4882a593Smuzhiyun gpio_request(GPIO_FN_PDSTATUS, NULL);
1119*4882a593Smuzhiyun
1120*4882a593Smuzhiyun /* enable SCIFA0 */
1121*4882a593Smuzhiyun gpio_request(GPIO_FN_SCIF0_TXD, NULL);
1122*4882a593Smuzhiyun gpio_request(GPIO_FN_SCIF0_RXD, NULL);
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun /* enable debug LED */
1125*4882a593Smuzhiyun gpio_request(GPIO_PTG0, NULL);
1126*4882a593Smuzhiyun gpio_request(GPIO_PTG1, NULL);
1127*4882a593Smuzhiyun gpio_request(GPIO_PTG2, NULL);
1128*4882a593Smuzhiyun gpio_request(GPIO_PTG3, NULL);
1129*4882a593Smuzhiyun gpio_direction_output(GPIO_PTG0, 0);
1130*4882a593Smuzhiyun gpio_direction_output(GPIO_PTG1, 0);
1131*4882a593Smuzhiyun gpio_direction_output(GPIO_PTG2, 0);
1132*4882a593Smuzhiyun gpio_direction_output(GPIO_PTG3, 0);
1133*4882a593Smuzhiyun __raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
1134*4882a593Smuzhiyun
1135*4882a593Smuzhiyun /* enable SH-Eth */
1136*4882a593Smuzhiyun gpio_request(GPIO_PTA1, NULL);
1137*4882a593Smuzhiyun gpio_direction_output(GPIO_PTA1, 1);
1138*4882a593Smuzhiyun mdelay(20);
1139*4882a593Smuzhiyun
1140*4882a593Smuzhiyun gpio_request(GPIO_FN_RMII_RXD0, NULL);
1141*4882a593Smuzhiyun gpio_request(GPIO_FN_RMII_RXD1, NULL);
1142*4882a593Smuzhiyun gpio_request(GPIO_FN_RMII_TXD0, NULL);
1143*4882a593Smuzhiyun gpio_request(GPIO_FN_RMII_TXD1, NULL);
1144*4882a593Smuzhiyun gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
1145*4882a593Smuzhiyun gpio_request(GPIO_FN_RMII_TX_EN, NULL);
1146*4882a593Smuzhiyun gpio_request(GPIO_FN_RMII_RX_ER, NULL);
1147*4882a593Smuzhiyun gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
1148*4882a593Smuzhiyun gpio_request(GPIO_FN_MDIO, NULL);
1149*4882a593Smuzhiyun gpio_request(GPIO_FN_MDC, NULL);
1150*4882a593Smuzhiyun gpio_request(GPIO_FN_LNKSTA, NULL);
1151*4882a593Smuzhiyun
1152*4882a593Smuzhiyun /* enable USB */
1153*4882a593Smuzhiyun __raw_writew(0x0000, 0xA4D80000);
1154*4882a593Smuzhiyun __raw_writew(0x0000, 0xA4D90000);
1155*4882a593Smuzhiyun gpio_request(GPIO_PTB3, NULL);
1156*4882a593Smuzhiyun gpio_request(GPIO_PTB4, NULL);
1157*4882a593Smuzhiyun gpio_request(GPIO_PTB5, NULL);
1158*4882a593Smuzhiyun gpio_direction_input(GPIO_PTB3);
1159*4882a593Smuzhiyun gpio_direction_output(GPIO_PTB4, 0);
1160*4882a593Smuzhiyun gpio_direction_output(GPIO_PTB5, 0);
1161*4882a593Smuzhiyun __raw_writew(0x0600, 0xa40501d4);
1162*4882a593Smuzhiyun __raw_writew(0x0600, 0xa4050192);
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun if (gpio_get_value(GPIO_PTB3)) {
1165*4882a593Smuzhiyun printk(KERN_INFO "USB1 function is selected\n");
1166*4882a593Smuzhiyun usb1_common_device.name = "r8a66597_udc";
1167*4882a593Smuzhiyun } else {
1168*4882a593Smuzhiyun printk(KERN_INFO "USB1 host is selected\n");
1169*4882a593Smuzhiyun usb1_common_device.name = "r8a66597_hcd";
1170*4882a593Smuzhiyun }
1171*4882a593Smuzhiyun
1172*4882a593Smuzhiyun /* enable LCDC */
1173*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD23, NULL);
1174*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD22, NULL);
1175*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD21, NULL);
1176*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD20, NULL);
1177*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD19, NULL);
1178*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD18, NULL);
1179*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD17, NULL);
1180*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD16, NULL);
1181*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD15, NULL);
1182*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD14, NULL);
1183*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD13, NULL);
1184*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD12, NULL);
1185*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD11, NULL);
1186*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD10, NULL);
1187*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD9, NULL);
1188*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD8, NULL);
1189*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD7, NULL);
1190*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD6, NULL);
1191*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD5, NULL);
1192*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD4, NULL);
1193*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD3, NULL);
1194*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD2, NULL);
1195*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD1, NULL);
1196*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDD0, NULL);
1197*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDDISP, NULL);
1198*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDHSYN, NULL);
1199*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDDCK, NULL);
1200*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDVSYN, NULL);
1201*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDDON, NULL);
1202*4882a593Smuzhiyun gpio_request(GPIO_FN_LCDLCLK, NULL);
1203*4882a593Smuzhiyun __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun gpio_request(GPIO_PTE6, NULL);
1206*4882a593Smuzhiyun gpio_request(GPIO_PTU1, NULL);
1207*4882a593Smuzhiyun gpio_request(GPIO_PTA2, NULL);
1208*4882a593Smuzhiyun gpio_direction_input(GPIO_PTE6);
1209*4882a593Smuzhiyun gpio_direction_output(GPIO_PTU1, 0);
1210*4882a593Smuzhiyun gpio_direction_output(GPIO_PTA2, 0);
1211*4882a593Smuzhiyun
1212*4882a593Smuzhiyun /* I/O buffer drive ability is high */
1213*4882a593Smuzhiyun __raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
1214*4882a593Smuzhiyun
1215*4882a593Smuzhiyun if (gpio_get_value(GPIO_PTE6)) {
1216*4882a593Smuzhiyun /* DVI */
1217*4882a593Smuzhiyun lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
1218*4882a593Smuzhiyun lcdc_info.ch[0].clock_divider = 1;
1219*4882a593Smuzhiyun lcdc_info.ch[0].lcd_modes = ecovec_dvi_modes;
1220*4882a593Smuzhiyun lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_dvi_modes);
1221*4882a593Smuzhiyun
1222*4882a593Smuzhiyun /* No backlight */
1223*4882a593Smuzhiyun gpio_backlight_data.fbdev = NULL;
1224*4882a593Smuzhiyun
1225*4882a593Smuzhiyun gpio_set_value(GPIO_PTA2, 1);
1226*4882a593Smuzhiyun gpio_set_value(GPIO_PTU1, 1);
1227*4882a593Smuzhiyun } else {
1228*4882a593Smuzhiyun /* Panel */
1229*4882a593Smuzhiyun lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
1230*4882a593Smuzhiyun lcdc_info.ch[0].clock_divider = 2;
1231*4882a593Smuzhiyun lcdc_info.ch[0].lcd_modes = ecovec_lcd_modes;
1232*4882a593Smuzhiyun lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_lcd_modes);
1233*4882a593Smuzhiyun
1234*4882a593Smuzhiyun /* FIXME
1235*4882a593Smuzhiyun *
1236*4882a593Smuzhiyun * LCDDON control is needed for Panel,
1237*4882a593Smuzhiyun * but current sh_mobile_lcdc driver doesn't control it.
1238*4882a593Smuzhiyun * It is temporary correspondence
1239*4882a593Smuzhiyun */
1240*4882a593Smuzhiyun gpio_request(GPIO_PTF4, NULL);
1241*4882a593Smuzhiyun gpio_direction_output(GPIO_PTF4, 1);
1242*4882a593Smuzhiyun
1243*4882a593Smuzhiyun /* enable TouchScreen */
1244*4882a593Smuzhiyun i2c_register_board_info(0, &ts_i2c_clients, 1);
1245*4882a593Smuzhiyun irq_set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW);
1246*4882a593Smuzhiyun }
1247*4882a593Smuzhiyun
1248*4882a593Smuzhiyun /* enable CEU0 */
1249*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D15, NULL);
1250*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D14, NULL);
1251*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D13, NULL);
1252*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D12, NULL);
1253*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D11, NULL);
1254*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D10, NULL);
1255*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D9, NULL);
1256*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D8, NULL);
1257*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D7, NULL);
1258*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D6, NULL);
1259*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D5, NULL);
1260*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D4, NULL);
1261*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D3, NULL);
1262*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D2, NULL);
1263*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D1, NULL);
1264*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_D0, NULL);
1265*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_VD, NULL);
1266*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_CLK, NULL);
1267*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_FLD, NULL);
1268*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO0_HD, NULL);
1269*4882a593Smuzhiyun
1270*4882a593Smuzhiyun /* enable CEU1 */
1271*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO1_D7, NULL);
1272*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO1_D6, NULL);
1273*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO1_D5, NULL);
1274*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO1_D4, NULL);
1275*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO1_D3, NULL);
1276*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO1_D2, NULL);
1277*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO1_D1, NULL);
1278*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO1_D0, NULL);
1279*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO1_FLD, NULL);
1280*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO1_HD, NULL);
1281*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO1_VD, NULL);
1282*4882a593Smuzhiyun gpio_request(GPIO_FN_VIO1_CLK, NULL);
1283*4882a593Smuzhiyun
1284*4882a593Smuzhiyun /* enable KEYSC */
1285*4882a593Smuzhiyun gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
1286*4882a593Smuzhiyun gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
1287*4882a593Smuzhiyun gpio_request(GPIO_FN_KEYOUT3, NULL);
1288*4882a593Smuzhiyun gpio_request(GPIO_FN_KEYOUT2, NULL);
1289*4882a593Smuzhiyun gpio_request(GPIO_FN_KEYOUT1, NULL);
1290*4882a593Smuzhiyun gpio_request(GPIO_FN_KEYOUT0, NULL);
1291*4882a593Smuzhiyun gpio_request(GPIO_FN_KEYIN0, NULL);
1292*4882a593Smuzhiyun
1293*4882a593Smuzhiyun /* enable user debug switch */
1294*4882a593Smuzhiyun gpio_request(GPIO_PTR0, NULL);
1295*4882a593Smuzhiyun gpio_request(GPIO_PTR4, NULL);
1296*4882a593Smuzhiyun gpio_request(GPIO_PTR5, NULL);
1297*4882a593Smuzhiyun gpio_request(GPIO_PTR6, NULL);
1298*4882a593Smuzhiyun gpio_direction_input(GPIO_PTR0);
1299*4882a593Smuzhiyun gpio_direction_input(GPIO_PTR4);
1300*4882a593Smuzhiyun gpio_direction_input(GPIO_PTR5);
1301*4882a593Smuzhiyun gpio_direction_input(GPIO_PTR6);
1302*4882a593Smuzhiyun
1303*4882a593Smuzhiyun /* SD-card slot CN11 */
1304*4882a593Smuzhiyun #if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
1305*4882a593Smuzhiyun /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */
1306*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI0WP, NULL);
1307*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI0CMD, NULL);
1308*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI0CLK, NULL);
1309*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI0D3, NULL);
1310*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI0D2, NULL);
1311*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI0D1, NULL);
1312*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI0D0, NULL);
1313*4882a593Smuzhiyun #else
1314*4882a593Smuzhiyun /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
1315*4882a593Smuzhiyun gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
1316*4882a593Smuzhiyun gpio_request(GPIO_FN_MSIOF0_RXD, NULL);
1317*4882a593Smuzhiyun gpio_request(GPIO_FN_MSIOF0_TSCK, NULL);
1318*4882a593Smuzhiyun gpio_request(GPIO_PTB6, NULL); /* 3.3V power control */
1319*4882a593Smuzhiyun gpio_direction_output(GPIO_PTB6, 0); /* disable power by default */
1320*4882a593Smuzhiyun
1321*4882a593Smuzhiyun gpiod_add_lookup_table(&mmc_spi_gpio_table);
1322*4882a593Smuzhiyun gpiod_add_lookup_table(&msiof_gpio_table);
1323*4882a593Smuzhiyun spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
1324*4882a593Smuzhiyun #endif
1325*4882a593Smuzhiyun
1326*4882a593Smuzhiyun /* MMC/SD-card slot CN12 */
1327*4882a593Smuzhiyun #if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
1328*4882a593Smuzhiyun /* enable MMCIF (needs DS2.6,7 set to OFF,ON) */
1329*4882a593Smuzhiyun gpio_request(GPIO_FN_MMC_D7, NULL);
1330*4882a593Smuzhiyun gpio_request(GPIO_FN_MMC_D6, NULL);
1331*4882a593Smuzhiyun gpio_request(GPIO_FN_MMC_D5, NULL);
1332*4882a593Smuzhiyun gpio_request(GPIO_FN_MMC_D4, NULL);
1333*4882a593Smuzhiyun gpio_request(GPIO_FN_MMC_D3, NULL);
1334*4882a593Smuzhiyun gpio_request(GPIO_FN_MMC_D2, NULL);
1335*4882a593Smuzhiyun gpio_request(GPIO_FN_MMC_D1, NULL);
1336*4882a593Smuzhiyun gpio_request(GPIO_FN_MMC_D0, NULL);
1337*4882a593Smuzhiyun gpio_request(GPIO_FN_MMC_CLK, NULL);
1338*4882a593Smuzhiyun gpio_request(GPIO_FN_MMC_CMD, NULL);
1339*4882a593Smuzhiyun
1340*4882a593Smuzhiyun cn12_enabled = true;
1341*4882a593Smuzhiyun #elif defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
1342*4882a593Smuzhiyun /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
1343*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI1WP, NULL);
1344*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI1CMD, NULL);
1345*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI1CLK, NULL);
1346*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI1D3, NULL);
1347*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI1D2, NULL);
1348*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI1D1, NULL);
1349*4882a593Smuzhiyun gpio_request(GPIO_FN_SDHI1D0, NULL);
1350*4882a593Smuzhiyun
1351*4882a593Smuzhiyun cn12_enabled = true;
1352*4882a593Smuzhiyun #endif
1353*4882a593Smuzhiyun
1354*4882a593Smuzhiyun if (cn12_enabled)
1355*4882a593Smuzhiyun /* I/O buffer drive ability is high for CN12 */
1356*4882a593Smuzhiyun __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000,
1357*4882a593Smuzhiyun IODRIVEA);
1358*4882a593Smuzhiyun
1359*4882a593Smuzhiyun /* enable FSI */
1360*4882a593Smuzhiyun gpio_request(GPIO_FN_FSIMCKB, NULL);
1361*4882a593Smuzhiyun gpio_request(GPIO_FN_FSIIBSD, NULL);
1362*4882a593Smuzhiyun gpio_request(GPIO_FN_FSIOBSD, NULL);
1363*4882a593Smuzhiyun gpio_request(GPIO_FN_FSIIBBCK, NULL);
1364*4882a593Smuzhiyun gpio_request(GPIO_FN_FSIIBLRCK, NULL);
1365*4882a593Smuzhiyun gpio_request(GPIO_FN_FSIOBBCK, NULL);
1366*4882a593Smuzhiyun gpio_request(GPIO_FN_FSIOBLRCK, NULL);
1367*4882a593Smuzhiyun gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
1368*4882a593Smuzhiyun
1369*4882a593Smuzhiyun /* set SPU2 clock to 83.4 MHz */
1370*4882a593Smuzhiyun clk = clk_get(NULL, "spu_clk");
1371*4882a593Smuzhiyun if (!IS_ERR(clk)) {
1372*4882a593Smuzhiyun clk_set_rate(clk, clk_round_rate(clk, 83333333));
1373*4882a593Smuzhiyun clk_put(clk);
1374*4882a593Smuzhiyun }
1375*4882a593Smuzhiyun
1376*4882a593Smuzhiyun /* change parent of FSI B */
1377*4882a593Smuzhiyun clk = clk_get(NULL, "fsib_clk");
1378*4882a593Smuzhiyun if (!IS_ERR(clk)) {
1379*4882a593Smuzhiyun /* 48kHz dummy clock was used to make sure 1/1 divide */
1380*4882a593Smuzhiyun clk_set_rate(&sh7724_fsimckb_clk, 48000);
1381*4882a593Smuzhiyun clk_set_parent(clk, &sh7724_fsimckb_clk);
1382*4882a593Smuzhiyun clk_set_rate(clk, 48000);
1383*4882a593Smuzhiyun clk_put(clk);
1384*4882a593Smuzhiyun }
1385*4882a593Smuzhiyun
1386*4882a593Smuzhiyun gpio_request(GPIO_PTU0, NULL);
1387*4882a593Smuzhiyun gpio_direction_output(GPIO_PTU0, 0);
1388*4882a593Smuzhiyun mdelay(20);
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun /* enable motion sensor */
1391*4882a593Smuzhiyun gpio_request(GPIO_FN_INTC_IRQ1, NULL);
1392*4882a593Smuzhiyun gpio_direction_input(GPIO_FN_INTC_IRQ1);
1393*4882a593Smuzhiyun
1394*4882a593Smuzhiyun /* set VPU clock to 166 MHz */
1395*4882a593Smuzhiyun clk = clk_get(NULL, "vpu_clk");
1396*4882a593Smuzhiyun if (!IS_ERR(clk)) {
1397*4882a593Smuzhiyun clk_set_rate(clk, clk_round_rate(clk, 166000000));
1398*4882a593Smuzhiyun clk_put(clk);
1399*4882a593Smuzhiyun }
1400*4882a593Smuzhiyun
1401*4882a593Smuzhiyun /* enable IrDA */
1402*4882a593Smuzhiyun gpio_request(GPIO_FN_IRDA_OUT, NULL);
1403*4882a593Smuzhiyun gpio_request(GPIO_FN_IRDA_IN, NULL);
1404*4882a593Smuzhiyun gpio_request(GPIO_PTU5, NULL);
1405*4882a593Smuzhiyun gpio_direction_output(GPIO_PTU5, 0);
1406*4882a593Smuzhiyun
1407*4882a593Smuzhiyun /* Register gpio lookup tables for cameras and video decoder */
1408*4882a593Smuzhiyun gpiod_add_lookup_table(&tw9910_gpios);
1409*4882a593Smuzhiyun gpiod_add_lookup_table(&mt9t112_0_gpios);
1410*4882a593Smuzhiyun gpiod_add_lookup_table(&mt9t112_1_gpios);
1411*4882a593Smuzhiyun
1412*4882a593Smuzhiyun /* enable I2C device */
1413*4882a593Smuzhiyun i2c_register_board_info(0, i2c0_devices,
1414*4882a593Smuzhiyun ARRAY_SIZE(i2c0_devices));
1415*4882a593Smuzhiyun
1416*4882a593Smuzhiyun i2c_register_board_info(1, i2c1_devices,
1417*4882a593Smuzhiyun ARRAY_SIZE(i2c1_devices));
1418*4882a593Smuzhiyun
1419*4882a593Smuzhiyun #if defined(CONFIG_VIDEO_SH_VOU) || defined(CONFIG_VIDEO_SH_VOU_MODULE)
1420*4882a593Smuzhiyun /* VOU */
1421*4882a593Smuzhiyun gpio_request(GPIO_FN_DV_D15, NULL);
1422*4882a593Smuzhiyun gpio_request(GPIO_FN_DV_D14, NULL);
1423*4882a593Smuzhiyun gpio_request(GPIO_FN_DV_D13, NULL);
1424*4882a593Smuzhiyun gpio_request(GPIO_FN_DV_D12, NULL);
1425*4882a593Smuzhiyun gpio_request(GPIO_FN_DV_D11, NULL);
1426*4882a593Smuzhiyun gpio_request(GPIO_FN_DV_D10, NULL);
1427*4882a593Smuzhiyun gpio_request(GPIO_FN_DV_D9, NULL);
1428*4882a593Smuzhiyun gpio_request(GPIO_FN_DV_D8, NULL);
1429*4882a593Smuzhiyun gpio_request(GPIO_FN_DV_CLKI, NULL);
1430*4882a593Smuzhiyun gpio_request(GPIO_FN_DV_CLK, NULL);
1431*4882a593Smuzhiyun gpio_request(GPIO_FN_DV_VSYNC, NULL);
1432*4882a593Smuzhiyun gpio_request(GPIO_FN_DV_HSYNC, NULL);
1433*4882a593Smuzhiyun
1434*4882a593Smuzhiyun /* AK8813 power / reset sequence */
1435*4882a593Smuzhiyun gpio_request(GPIO_PTG4, NULL);
1436*4882a593Smuzhiyun gpio_request(GPIO_PTU3, NULL);
1437*4882a593Smuzhiyun /* Reset */
1438*4882a593Smuzhiyun gpio_direction_output(GPIO_PTG4, 0);
1439*4882a593Smuzhiyun /* Power down */
1440*4882a593Smuzhiyun gpio_direction_output(GPIO_PTU3, 1);
1441*4882a593Smuzhiyun
1442*4882a593Smuzhiyun udelay(10);
1443*4882a593Smuzhiyun
1444*4882a593Smuzhiyun /* Power up, reset */
1445*4882a593Smuzhiyun gpio_set_value(GPIO_PTU3, 0);
1446*4882a593Smuzhiyun
1447*4882a593Smuzhiyun udelay(10);
1448*4882a593Smuzhiyun
1449*4882a593Smuzhiyun /* Remove reset */
1450*4882a593Smuzhiyun gpio_set_value(GPIO_PTG4, 1);
1451*4882a593Smuzhiyun #endif
1452*4882a593Smuzhiyun
1453*4882a593Smuzhiyun /* Initialize CEU platform devices separately to map memory first */
1454*4882a593Smuzhiyun device_initialize(&ecovec_ceu_devices[0]->dev);
1455*4882a593Smuzhiyun dma_declare_coherent_memory(&ecovec_ceu_devices[0]->dev,
1456*4882a593Smuzhiyun ceu0_dma_membase, ceu0_dma_membase,
1457*4882a593Smuzhiyun ceu0_dma_membase +
1458*4882a593Smuzhiyun CEU_BUFFER_MEMORY_SIZE - 1);
1459*4882a593Smuzhiyun platform_device_add(ecovec_ceu_devices[0]);
1460*4882a593Smuzhiyun
1461*4882a593Smuzhiyun device_initialize(&ecovec_ceu_devices[1]->dev);
1462*4882a593Smuzhiyun dma_declare_coherent_memory(&ecovec_ceu_devices[1]->dev,
1463*4882a593Smuzhiyun ceu1_dma_membase, ceu1_dma_membase,
1464*4882a593Smuzhiyun ceu1_dma_membase +
1465*4882a593Smuzhiyun CEU_BUFFER_MEMORY_SIZE - 1);
1466*4882a593Smuzhiyun platform_device_add(ecovec_ceu_devices[1]);
1467*4882a593Smuzhiyun
1468*4882a593Smuzhiyun gpiod_add_lookup_table(&cn12_power_gpiod_table);
1469*4882a593Smuzhiyun #if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
1470*4882a593Smuzhiyun gpiod_add_lookup_table(&sdhi0_power_gpiod_table);
1471*4882a593Smuzhiyun gpiod_add_lookup_table(&sdhi0_gpio_table);
1472*4882a593Smuzhiyun #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
1473*4882a593Smuzhiyun gpiod_add_lookup_table(&sdhi1_gpio_table);
1474*4882a593Smuzhiyun #endif
1475*4882a593Smuzhiyun #endif
1476*4882a593Smuzhiyun
1477*4882a593Smuzhiyun gpiod_add_lookup_table(&gpio_backlight_lookup);
1478*4882a593Smuzhiyun gpio_backlight_device = platform_device_register_full(
1479*4882a593Smuzhiyun &gpio_backlight_device_info);
1480*4882a593Smuzhiyun if (IS_ERR(gpio_backlight_device))
1481*4882a593Smuzhiyun return PTR_ERR(gpio_backlight_device);
1482*4882a593Smuzhiyun
1483*4882a593Smuzhiyun return platform_add_devices(ecovec_devices,
1484*4882a593Smuzhiyun ARRAY_SIZE(ecovec_devices));
1485*4882a593Smuzhiyun }
1486*4882a593Smuzhiyun arch_initcall(arch_setup);
1487*4882a593Smuzhiyun
devices_setup(void)1488*4882a593Smuzhiyun static int __init devices_setup(void)
1489*4882a593Smuzhiyun {
1490*4882a593Smuzhiyun sh_eth_init(&sh_eth_plat);
1491*4882a593Smuzhiyun return 0;
1492*4882a593Smuzhiyun }
1493*4882a593Smuzhiyun device_initcall(devices_setup);
1494*4882a593Smuzhiyun
1495*4882a593Smuzhiyun /* Reserve a portion of memory for CEU 0 and CEU 1 buffers */
ecovec_mv_mem_reserve(void)1496*4882a593Smuzhiyun static void __init ecovec_mv_mem_reserve(void)
1497*4882a593Smuzhiyun {
1498*4882a593Smuzhiyun phys_addr_t phys;
1499*4882a593Smuzhiyun phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
1500*4882a593Smuzhiyun
1501*4882a593Smuzhiyun phys = memblock_phys_alloc(size, PAGE_SIZE);
1502*4882a593Smuzhiyun if (!phys)
1503*4882a593Smuzhiyun panic("Failed to allocate CEU0 memory\n");
1504*4882a593Smuzhiyun
1505*4882a593Smuzhiyun memblock_free(phys, size);
1506*4882a593Smuzhiyun memblock_remove(phys, size);
1507*4882a593Smuzhiyun ceu0_dma_membase = phys;
1508*4882a593Smuzhiyun
1509*4882a593Smuzhiyun phys = memblock_phys_alloc(size, PAGE_SIZE);
1510*4882a593Smuzhiyun if (!phys)
1511*4882a593Smuzhiyun panic("Failed to allocate CEU1 memory\n");
1512*4882a593Smuzhiyun
1513*4882a593Smuzhiyun memblock_free(phys, size);
1514*4882a593Smuzhiyun memblock_remove(phys, size);
1515*4882a593Smuzhiyun ceu1_dma_membase = phys;
1516*4882a593Smuzhiyun }
1517*4882a593Smuzhiyun
1518*4882a593Smuzhiyun static struct sh_machine_vector mv_ecovec __initmv = {
1519*4882a593Smuzhiyun .mv_name = "R0P7724 (EcoVec)",
1520*4882a593Smuzhiyun .mv_mem_reserve = ecovec_mv_mem_reserve,
1521*4882a593Smuzhiyun };
1522