1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/sh/boards/dreamcast/irq.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Holly IRQ support for the Sega Dreamcast.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This file is part of the LinuxDC project (www.linuxdc.org)
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/export.h>
14*4882a593Smuzhiyun #include <linux/err.h>
15*4882a593Smuzhiyun #include <mach/sysasic.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * Dreamcast System ASIC Hardware Events -
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
21*4882a593Smuzhiyun * hardware events from system peripherals and triggering an SH7750 IRQ.
22*4882a593Smuzhiyun * Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
23*4882a593Smuzhiyun * set in the Event Mask Registers (EMRs). When a hardware event is
24*4882a593Smuzhiyun * triggered, its corresponding bit in the Event Status Registers (ESRs)
25*4882a593Smuzhiyun * is set, and that bit should be rewritten to the ESR to acknowledge that
26*4882a593Smuzhiyun * event.
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908. Event
29*4882a593Smuzhiyun * types can be found in arch/sh/include/mach-dreamcast/mach/sysasic.h.
30*4882a593Smuzhiyun * There are three groups of EMRs that parallel the ESRs. Each EMR group
31*4882a593Smuzhiyun * corresponds to an IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13,
32*4882a593Smuzhiyun * 0xa05f6920 - 0xa05f6928 triggers IRQ 11, and 0xa05f6930 - 0xa05f6938
33*4882a593Smuzhiyun * triggers IRQ 9.
34*4882a593Smuzhiyun *
35*4882a593Smuzhiyun * In the kernel, these events are mapped to virtual IRQs so that drivers can
36*4882a593Smuzhiyun * respond to them as they would a normal interrupt. In order to keep this
37*4882a593Smuzhiyun * mapping simple, the events are mapped as:
38*4882a593Smuzhiyun *
39*4882a593Smuzhiyun * 6900/6910 - Events 0-31, IRQ 13
40*4882a593Smuzhiyun * 6904/6924 - Events 32-63, IRQ 11
41*4882a593Smuzhiyun * 6908/6938 - Events 64-95, IRQ 9
42*4882a593Smuzhiyun *
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define ESR_BASE 0x005f6900 /* Base event status register */
46*4882a593Smuzhiyun #define EMR_BASE 0x005f6910 /* Base event mask register */
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * Helps us determine the EMR group that this event belongs to: 0 = 0x6910,
50*4882a593Smuzhiyun * 1 = 0x6920, 2 = 0x6930; also determine the event offset.
51*4882a593Smuzhiyun */
52*4882a593Smuzhiyun #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* Return the hardware event's bit position within the EMR/ESR */
55*4882a593Smuzhiyun #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /*
58*4882a593Smuzhiyun * For each of these *_irq routines, the IRQ passed in is the virtual IRQ
59*4882a593Smuzhiyun * (logically mapped to the corresponding bit for the hardware event).
60*4882a593Smuzhiyun */
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Disable the hardware event by masking its bit in its EMR */
disable_systemasic_irq(struct irq_data * data)63*4882a593Smuzhiyun static inline void disable_systemasic_irq(struct irq_data *data)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun unsigned int irq = data->irq;
66*4882a593Smuzhiyun __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
67*4882a593Smuzhiyun __u32 mask;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun mask = inl(emr);
70*4882a593Smuzhiyun mask &= ~(1 << EVENT_BIT(irq));
71*4882a593Smuzhiyun outl(mask, emr);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Enable the hardware event by setting its bit in its EMR */
enable_systemasic_irq(struct irq_data * data)75*4882a593Smuzhiyun static inline void enable_systemasic_irq(struct irq_data *data)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun unsigned int irq = data->irq;
78*4882a593Smuzhiyun __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
79*4882a593Smuzhiyun __u32 mask;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun mask = inl(emr);
82*4882a593Smuzhiyun mask |= (1 << EVENT_BIT(irq));
83*4882a593Smuzhiyun outl(mask, emr);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* Acknowledge a hardware event by writing its bit back to its ESR */
mask_ack_systemasic_irq(struct irq_data * data)87*4882a593Smuzhiyun static void mask_ack_systemasic_irq(struct irq_data *data)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun unsigned int irq = data->irq;
90*4882a593Smuzhiyun __u32 esr = ESR_BASE + (LEVEL(irq) << 2);
91*4882a593Smuzhiyun disable_systemasic_irq(data);
92*4882a593Smuzhiyun outl((1 << EVENT_BIT(irq)), esr);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun struct irq_chip systemasic_int = {
96*4882a593Smuzhiyun .name = "System ASIC",
97*4882a593Smuzhiyun .irq_mask = disable_systemasic_irq,
98*4882a593Smuzhiyun .irq_mask_ack = mask_ack_systemasic_irq,
99*4882a593Smuzhiyun .irq_unmask = enable_systemasic_irq,
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /*
103*4882a593Smuzhiyun * Map the hardware event indicated by the processor IRQ to a virtual IRQ.
104*4882a593Smuzhiyun */
systemasic_irq_demux(int irq)105*4882a593Smuzhiyun int systemasic_irq_demux(int irq)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun __u32 emr, esr, status, level;
108*4882a593Smuzhiyun __u32 j, bit;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun switch (irq) {
111*4882a593Smuzhiyun case 13:
112*4882a593Smuzhiyun level = 0;
113*4882a593Smuzhiyun break;
114*4882a593Smuzhiyun case 11:
115*4882a593Smuzhiyun level = 1;
116*4882a593Smuzhiyun break;
117*4882a593Smuzhiyun case 9:
118*4882a593Smuzhiyun level = 2;
119*4882a593Smuzhiyun break;
120*4882a593Smuzhiyun default:
121*4882a593Smuzhiyun return irq;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun emr = EMR_BASE + (level << 4) + (level << 2);
124*4882a593Smuzhiyun esr = ESR_BASE + (level << 2);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /* Mask the ESR to filter any spurious, unwanted interrupts */
127*4882a593Smuzhiyun status = inl(esr);
128*4882a593Smuzhiyun status &= inl(emr);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* Now scan and find the first set bit as the event to map */
131*4882a593Smuzhiyun for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
132*4882a593Smuzhiyun if (status & bit) {
133*4882a593Smuzhiyun irq = HW_EVENT_IRQ_BASE + j + (level << 5);
134*4882a593Smuzhiyun return irq;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /* Not reached */
139*4882a593Smuzhiyun return irq;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
systemasic_irq_init(void)142*4882a593Smuzhiyun void systemasic_irq_init(void)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun int irq_base, i;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE,
147*4882a593Smuzhiyun HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1);
148*4882a593Smuzhiyun if (IS_ERR_VALUE(irq_base)) {
149*4882a593Smuzhiyun pr_err("%s: failed hooking irqs\n", __func__);
150*4882a593Smuzhiyun return;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
154*4882a593Smuzhiyun irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq);
155*4882a593Smuzhiyun }
156