1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * June 2006 Steve Glendinning <steve.glendinning@shawell.net>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Polaris-specific resource declaration
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/regulator/fixed.h>
14*4882a593Smuzhiyun #include <linux/regulator/machine.h>
15*4882a593Smuzhiyun #include <linux/smsc911x.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <asm/irq.h>
18*4882a593Smuzhiyun #include <asm/machvec.h>
19*4882a593Smuzhiyun #include <asm/heartbeat.h>
20*4882a593Smuzhiyun #include <cpu/gpio.h>
21*4882a593Smuzhiyun #include <mach-se/mach/se.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define BCR2 (0xFFFFFF62)
24*4882a593Smuzhiyun #define WCR2 (0xFFFFFF66)
25*4882a593Smuzhiyun #define AREA5_WAIT_CTRL (0x1C00)
26*4882a593Smuzhiyun #define WAIT_STATES_10 (0x7)
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Dummy supplies, where voltage doesn't matter */
29*4882a593Smuzhiyun static struct regulator_consumer_supply dummy_supplies[] = {
30*4882a593Smuzhiyun REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
31*4882a593Smuzhiyun REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static struct resource smsc911x_resources[] = {
35*4882a593Smuzhiyun [0] = {
36*4882a593Smuzhiyun .name = "smsc911x-memory",
37*4882a593Smuzhiyun .start = PA_EXT5,
38*4882a593Smuzhiyun .end = PA_EXT5 + 0x1fff,
39*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
40*4882a593Smuzhiyun },
41*4882a593Smuzhiyun [1] = {
42*4882a593Smuzhiyun .name = "smsc911x-irq",
43*4882a593Smuzhiyun .start = IRQ0_IRQ,
44*4882a593Smuzhiyun .end = IRQ0_IRQ,
45*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
46*4882a593Smuzhiyun },
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static struct smsc911x_platform_config smsc911x_config = {
50*4882a593Smuzhiyun .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
51*4882a593Smuzhiyun .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
52*4882a593Smuzhiyun .flags = SMSC911X_USE_32BIT,
53*4882a593Smuzhiyun .phy_interface = PHY_INTERFACE_MODE_MII,
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static struct platform_device smsc911x_device = {
57*4882a593Smuzhiyun .name = "smsc911x",
58*4882a593Smuzhiyun .id = 0,
59*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(smsc911x_resources),
60*4882a593Smuzhiyun .resource = smsc911x_resources,
61*4882a593Smuzhiyun .dev = {
62*4882a593Smuzhiyun .platform_data = &smsc911x_config,
63*4882a593Smuzhiyun },
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun static struct heartbeat_data heartbeat_data = {
69*4882a593Smuzhiyun .bit_pos = heartbeat_bit_pos,
70*4882a593Smuzhiyun .nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static struct resource heartbeat_resource = {
74*4882a593Smuzhiyun .start = PORT_PCDR,
75*4882a593Smuzhiyun .end = PORT_PCDR,
76*4882a593Smuzhiyun .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static struct platform_device heartbeat_device = {
80*4882a593Smuzhiyun .name = "heartbeat",
81*4882a593Smuzhiyun .id = -1,
82*4882a593Smuzhiyun .dev = {
83*4882a593Smuzhiyun .platform_data = &heartbeat_data,
84*4882a593Smuzhiyun },
85*4882a593Smuzhiyun .num_resources = 1,
86*4882a593Smuzhiyun .resource = &heartbeat_resource,
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static struct platform_device *polaris_devices[] __initdata = {
90*4882a593Smuzhiyun &smsc911x_device,
91*4882a593Smuzhiyun &heartbeat_device,
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
polaris_initialise(void)94*4882a593Smuzhiyun static int __init polaris_initialise(void)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun u16 wcr, bcr_mask;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun printk(KERN_INFO "Configuring Polaris external bus\n");
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* Configure area 5 with 2 wait states */
103*4882a593Smuzhiyun wcr = __raw_readw(WCR2);
104*4882a593Smuzhiyun wcr &= (~AREA5_WAIT_CTRL);
105*4882a593Smuzhiyun wcr |= (WAIT_STATES_10 << 10);
106*4882a593Smuzhiyun __raw_writew(wcr, WCR2);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* Configure area 5 for 32-bit access */
109*4882a593Smuzhiyun bcr_mask = __raw_readw(BCR2);
110*4882a593Smuzhiyun bcr_mask |= 1 << 10;
111*4882a593Smuzhiyun __raw_writew(bcr_mask, BCR2);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun return platform_add_devices(polaris_devices,
114*4882a593Smuzhiyun ARRAY_SIZE(polaris_devices));
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun arch_initcall(polaris_initialise);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun static struct ipr_data ipr_irq_table[] = {
119*4882a593Smuzhiyun /* External IRQs */
120*4882a593Smuzhiyun { IRQ0_IRQ, 0, 0, 1, }, /* IRQ0 */
121*4882a593Smuzhiyun { IRQ1_IRQ, 0, 4, 1, }, /* IRQ1 */
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun static unsigned long ipr_offsets[] = {
125*4882a593Smuzhiyun INTC_IPRC
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun static struct ipr_desc ipr_irq_desc = {
129*4882a593Smuzhiyun .ipr_offsets = ipr_offsets,
130*4882a593Smuzhiyun .nr_offsets = ARRAY_SIZE(ipr_offsets),
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun .ipr_data = ipr_irq_table,
133*4882a593Smuzhiyun .nr_irqs = ARRAY_SIZE(ipr_irq_table),
134*4882a593Smuzhiyun .chip = {
135*4882a593Smuzhiyun .name = "sh7709-ext",
136*4882a593Smuzhiyun },
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun
init_polaris_irq(void)139*4882a593Smuzhiyun static void __init init_polaris_irq(void)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun /* Disable all interrupts */
142*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRA);
143*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRB);
144*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRC);
145*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRD);
146*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRE);
147*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRF);
148*4882a593Smuzhiyun __raw_writew(0, BCR_ILCRG);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun register_ipr_controller(&ipr_irq_desc);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun static struct sh_machine_vector mv_polaris __initmv = {
154*4882a593Smuzhiyun .mv_name = "Polaris",
155*4882a593Smuzhiyun .mv_init_irq = init_polaris_irq,
156*4882a593Smuzhiyun };
157