1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ALPHAPROJECT AP-SH4AD-0A Support.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2010 ALPHAPROJECT Co.,Ltd.
6*4882a593Smuzhiyun * Copyright (C) 2010 Matt Fleming
7*4882a593Smuzhiyun * Copyright (C) 2010 Paul Mundt
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/regulator/fixed.h>
13*4882a593Smuzhiyun #include <linux/regulator/machine.h>
14*4882a593Smuzhiyun #include <linux/smsc911x.h>
15*4882a593Smuzhiyun #include <linux/irq.h>
16*4882a593Smuzhiyun #include <linux/clk.h>
17*4882a593Smuzhiyun #include <asm/machvec.h>
18*4882a593Smuzhiyun #include <linux/sizes.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* Dummy supplies, where voltage doesn't matter */
21*4882a593Smuzhiyun static struct regulator_consumer_supply dummy_supplies[] = {
22*4882a593Smuzhiyun REGULATOR_SUPPLY("vddvario", "smsc911x"),
23*4882a593Smuzhiyun REGULATOR_SUPPLY("vdd33a", "smsc911x"),
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static struct resource smsc911x_resources[] = {
27*4882a593Smuzhiyun [0] = {
28*4882a593Smuzhiyun .name = "smsc911x-memory",
29*4882a593Smuzhiyun .start = 0xA4000000,
30*4882a593Smuzhiyun .end = 0xA4000000 + SZ_256 - 1,
31*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
32*4882a593Smuzhiyun },
33*4882a593Smuzhiyun [1] = {
34*4882a593Smuzhiyun .name = "smsc911x-irq",
35*4882a593Smuzhiyun .start = evt2irq(0x200),
36*4882a593Smuzhiyun .end = evt2irq(0x200),
37*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
38*4882a593Smuzhiyun },
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun static struct smsc911x_platform_config smsc911x_config = {
42*4882a593Smuzhiyun .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
43*4882a593Smuzhiyun .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
44*4882a593Smuzhiyun .flags = SMSC911X_USE_16BIT,
45*4882a593Smuzhiyun .phy_interface = PHY_INTERFACE_MODE_MII,
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun static struct platform_device smsc911x_device = {
49*4882a593Smuzhiyun .name = "smsc911x",
50*4882a593Smuzhiyun .id = -1,
51*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(smsc911x_resources),
52*4882a593Smuzhiyun .resource = smsc911x_resources,
53*4882a593Smuzhiyun .dev = {
54*4882a593Smuzhiyun .platform_data = &smsc911x_config,
55*4882a593Smuzhiyun },
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static struct platform_device *apsh4ad0a_devices[] __initdata = {
59*4882a593Smuzhiyun &smsc911x_device,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
apsh4ad0a_devices_setup(void)62*4882a593Smuzhiyun static int __init apsh4ad0a_devices_setup(void)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun return platform_add_devices(apsh4ad0a_devices,
67*4882a593Smuzhiyun ARRAY_SIZE(apsh4ad0a_devices));
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun device_initcall(apsh4ad0a_devices_setup);
70*4882a593Smuzhiyun
apsh4ad0a_mode_pins(void)71*4882a593Smuzhiyun static int apsh4ad0a_mode_pins(void)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun int value = 0;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* These are the factory default settings of SW1 and SW2.
76*4882a593Smuzhiyun * If you change these dip switches then you will need to
77*4882a593Smuzhiyun * adjust the values below as well.
78*4882a593Smuzhiyun */
79*4882a593Smuzhiyun value |= MODE_PIN0; /* Clock Mode 3 */
80*4882a593Smuzhiyun value |= MODE_PIN1;
81*4882a593Smuzhiyun value &= ~MODE_PIN2;
82*4882a593Smuzhiyun value &= ~MODE_PIN3;
83*4882a593Smuzhiyun value &= ~MODE_PIN4; /* 16-bit Area0 bus width */
84*4882a593Smuzhiyun value |= MODE_PIN5;
85*4882a593Smuzhiyun value |= MODE_PIN6;
86*4882a593Smuzhiyun value |= MODE_PIN7; /* Normal mode */
87*4882a593Smuzhiyun value |= MODE_PIN8; /* Little Endian */
88*4882a593Smuzhiyun value |= MODE_PIN9; /* Crystal resonator */
89*4882a593Smuzhiyun value &= ~MODE_PIN10; /* 29-bit address mode */
90*4882a593Smuzhiyun value &= ~MODE_PIN11; /* PCI-E Root port */
91*4882a593Smuzhiyun value &= ~MODE_PIN12; /* 4 lane + 1 lane */
92*4882a593Smuzhiyun value |= MODE_PIN13; /* AUD Enable */
93*4882a593Smuzhiyun value &= ~MODE_PIN14; /* Normal Operation */
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return value;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
apsh4ad0a_clk_init(void)98*4882a593Smuzhiyun static int apsh4ad0a_clk_init(void)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun struct clk *clk;
101*4882a593Smuzhiyun int ret;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun clk = clk_get(NULL, "extal");
104*4882a593Smuzhiyun if (IS_ERR(clk))
105*4882a593Smuzhiyun return PTR_ERR(clk);
106*4882a593Smuzhiyun ret = clk_set_rate(clk, 33333000);
107*4882a593Smuzhiyun clk_put(clk);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return ret;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* Initialize the board */
apsh4ad0a_setup(char ** cmdline_p)113*4882a593Smuzhiyun static void __init apsh4ad0a_setup(char **cmdline_p)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun pr_info("Alpha Project AP-SH4AD-0A support:\n");
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
apsh4ad0a_init_irq(void)118*4882a593Smuzhiyun static void __init apsh4ad0a_init_irq(void)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun plat_irq_setup_pins(IRQ_MODE_IRQ3210);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /*
124*4882a593Smuzhiyun * The Machine Vector
125*4882a593Smuzhiyun */
126*4882a593Smuzhiyun static struct sh_machine_vector mv_apsh4ad0a __initmv = {
127*4882a593Smuzhiyun .mv_name = "AP-SH4AD-0A",
128*4882a593Smuzhiyun .mv_setup = apsh4ad0a_setup,
129*4882a593Smuzhiyun .mv_mode_pins = apsh4ad0a_mode_pins,
130*4882a593Smuzhiyun .mv_clk_init = apsh4ad0a_clk_init,
131*4882a593Smuzhiyun .mv_init_irq = apsh4ad0a_init_irq,
132*4882a593Smuzhiyun };
133